[PATCHv2,18/25] arm: mach-k3: Add platform data for j721e and j7200

Message ID	20201120112326.10350-19-t-kristo@ti.com
State	Changes Requested
Delegated to:	Lokesh Vutla
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Tero Kristo <t-kristo@ti.com> To: <u-boot@lists.denx.de>, <lokeshvutla@ti.com> CC: <trini@konsulko.com>, <lukma@denx.de>, <praneeth@ti.com>, <d-gerlach@ti.com> Subject: [PATCHv2 18/25] arm: mach-k3: Add platform data for j721e and j7200 Date: Fri, 20 Nov 2020 13:23:19 +0200 Message-ID: <20201120112326.10350-19-t-kristo@ti.com> In-Reply-To: <20201120112326.10350-1-t-kristo@ti.com> References: <20201120112326.10350-1-t-kristo@ti.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	J72xx: HSM rearch support series \| expand [PATCHv2,00/25] J72xx: HSM rearch support series [PATCHv2,01/25] lib: rational: copy the rational fraction lib routines from Linux [PATCHv2,02/25] ram: k3-j721e: fix clk_set_rate API usage [PATCHv2,03/25] arm: mach-k3: introduce new config option for sysfw split [PATCHv2,04/25] remoteproc: k3-r5: remove sysfw PM calls if not supported [PATCHv2,05/25] common: fit: Update board_fit_image_post_process() to pass fit and node_offset [PATCHv2,06/25] clk: fixed_rate: add API for directly registering fixed rate clocks [PATCHv2,07/25] clk: fix clock tree dump to properly dump out every registered clock [PATCHv2,08/25] clk: do not attempt to fetch clock pointer with null device [PATCHv2,09/25] clk: add support for setting clk rate from cmdline [PATCHv2,10/25] clk: sci-clk: fix return value of set_rate [PATCHv2,11/25] clk: fix assigned-clocks to pass with deferring provider [PATCHv2,12/25] clk: fix set_rate to clean up cached rates for the hierarchy [PATCHv2,13/25] clk: add support for TI K3 SoC PLL [PATCHv2,14/25] clk: add support for TI K3 SoC clocks [PATCHv2,15/25] power: domain: Introduce driver for raw TI K3 PDs [PATCHv2,16/25] cmd: ti: pd: Add debug command for K3 power domains [PATCHv2,17/25] tools: k3_fit_atf: add DM binary to the FIT image [PATCHv2,18/25] arm: mach-k3: Add platform data for j721e and j7200 [PATCHv2,19/25] arm: mach-k3: add support for detecting firmware images from FIT [PATCHv2,20/25] arm: mach-k3: do board config for PM and RM only if supported [PATCHv2,21/25] arm: mach-k3: common: Drop main r5 start [PATCHv2,22/25] arm: mach-k3: sysfw-loader: pass boardcfg to sciserver [PATCHv2,23/25] configs: j721e_evm_r5: Enable raw access power management features [PATCHv2,24/25] configs: j7200_evm_r5: Enable raw access power management features [PATCHv2,25/25] board: ti: j72xx: README: update build instructions and image formats

diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 7572f56925..534ddfcd49 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -4,7 +4,7 @@ # Lokesh Vutla <lokeshvutla@ti.com> obj-$(CONFIG_SOC_K3_AM6) += am6_init.o -obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o +obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/ obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-$(CONFIG_TI_SECURE_DEVICE) += security.o diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile new file mode 100644 index 0000000000..ff9abd78ea --- /dev/null +++ b/arch/arm/mach-k3/j7200/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c new file mode 100644 index 0000000000..f5bdbdd55e --- /dev/null +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific clock platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv2_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv2_16fft_main_0_hsdivout6_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 1, 0x43008084, 0, 1, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 1, 0x40f08030, 4, 1, 0), + CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0), + CLK_PLL("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 1, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 1, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 1, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 1, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 1, 0x430080a0, 0, 1, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 4, 0x108030, 0, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 2, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), +}; + +const struct ti_k3_clk_platdata j7200_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 63, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 61, +}; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c new file mode 100644 index 0000000000..6c0ee688e0 --- /dev/null +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J7200 specific device platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]), + [2] = PSC_PD(14, &soc_psc_list[0], NULL), + [3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]), + [4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]), + [5] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[13]), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL), + [7] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL), + [8] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[7]), + [9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]), + [10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[7]), + [11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL), + [12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL), + [13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL), + [14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(8, &soc_lpsc_list[3]), + PSC_DEV(92, &soc_lpsc_list[4]), + PSC_DEV(91, &soc_lpsc_list[5]), + PSC_DEV(146, &soc_lpsc_list[6]), + PSC_DEV(4, &soc_lpsc_list[7]), + PSC_DEV(4, &soc_lpsc_list[8]), + PSC_DEV(202, &soc_lpsc_list[9]), + PSC_DEV(203, &soc_lpsc_list[10]), + PSC_DEV(103, &soc_lpsc_list[11]), + PSC_DEV(104, &soc_lpsc_list[11]), + PSC_DEV(154, &soc_lpsc_list[11]), + PSC_DEV(149, &soc_lpsc_list[11]), + PSC_DEV(197, &soc_lpsc_list[12]), + PSC_DEV(103, &soc_lpsc_list[13]), + PSC_DEV(104, &soc_lpsc_list[14]), +}; + +const struct ti_k3_pd_platdata j7200_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 6, + .num_lpsc = 15, + .num_devs = 18, +}; diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile new file mode 100644 index 0000000000..ff9abd78ea --- /dev/null +++ b/arch/arm/mach-k3/j721e/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ +obj-y += clk-data.o +obj-y += dev-data.o diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c new file mode 100644 index 0000000000..455cb81a56 --- /dev/null +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific clock platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-clk.h" + +static const char * const gluelogic_hfosc0_clkout_parents[] = { + "osc_19_2_mhz", + "osc_20_mhz", + "osc_24_mhz", + "osc_25_mhz", + "osc_26_mhz", + "osc_27_mhz", +}; + +static const char * const main_pll_hfosc_sel_out1_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const mcu_ospi0_iclk_sel_out0_parents[] = { + "fss_mcu_0_ospi_0_ospi_oclk_clk", +}; + +static const char * const mcu_ospi1_iclk_sel_out0_parents[] = { + "fss_mcu_0_ospi_1_ospi_oclk_clk", +}; + +static const char * const wkup_fref_clksel_out0_parents[] = { + "gluelogic_hfosc0_clkout", + "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", +}; + +static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = { + "wkup_fref_clksel_out0", + "hsdiv1_16fft_mcu_0_hsdivout0_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout4_clk", + "hsdiv4_16fft_mcu_2_hsdivout4_clk", +}; + +static const char * const mcuusart_clk_sel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "postdiv3_16fft_main_1_hsdivout5_clk", +}; + +static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = { + "hsdiv4_16fft_mcu_1_hsdivout3_clk", + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out0_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out12_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out2_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out3_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out7_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const main_pll_hfosc_sel_out8_parents[] = { + "gluelogic_hfosc0_clkout", +}; + +static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = { + "main_pll_hfosc_sel_out0", + "hsdiv4_16fft_main_0_hsdivout0_clk", +}; + +static const char * const emmcsd_refclk_sel_out0_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const emmcsd_refclk_sel_out1_parents[] = { + "hsdiv4_16fft_main_0_hsdivout2_clk", + "hsdiv4_16fft_main_1_hsdivout2_clk", + "hsdiv4_16fft_main_2_hsdivout2_clk", + "hsdiv4_16fft_main_3_hsdivout2_clk", +}; + +static const char * const gtc_clk_mux_out0_parents[] = { + "hsdiv4_16fft_main_3_hsdivout1_clk", + "postdiv3_16fft_main_0_hsdivout6_clk", + "hsdiv4_16fft_mcu_2_hsdivout1_clk", + "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", +}; + +static const struct clk_data clk_list[] = { + CLK_FIXED_RATE("osc_27_mhz", 27000000, 0), + CLK_FIXED_RATE("osc_26_mhz", 26000000, 0), + CLK_FIXED_RATE("osc_25_mhz", 25000000, 0), + CLK_FIXED_RATE("osc_24_mhz", 24000000, 0), + CLK_FIXED_RATE("osc_20_mhz", 20000000, 0), + CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0), + CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0), + CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 1, 0x43008084, 0, 1, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0), + CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0), + CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 1, 0x40f08030, 4, 1, 0), + CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 1, 0x40f08034, 4, 1, 0), + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0), + CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0), + CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0), + CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0), + CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0), + CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 1, 0x43008080, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 1, 0x430080b0, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 1, 0x43008088, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 1, 0x4300808c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 1, 0x4300809c, 0, 1, 0), + CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 1, 0x430080a0, 0, 1, 0), + CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0), + CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000), + CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0), + CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0), + CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0), + CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0), + CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000), + CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0), + CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0), + CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0), + CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0), + CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0), + CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0), + CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 4, 0x108030, 0, 4, 0), + CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0), + CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0), +}; + +static const struct dev_clk soc_dev_clk_data[] = { + DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"), + DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"), + DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"), + DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"), + DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"), + DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"), + DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 1, "gtc_clk_mux_out0"), + DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"), + DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"), + DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"), + DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"), + DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"), + DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"), + DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"), + DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"), + DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"), + DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"), + DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"), + DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"), + DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"), + DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"), + DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"), + DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"), + DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"), + DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"), + DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"), + DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(149, 0, "mcuusart_clk_sel_out0"), + DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"), + DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"), + DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), + DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"), + DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"), + DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"), + DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), +}; + +const struct ti_k3_clk_platdata j721e_clk_platdata = { + .clk_list = clk_list, + .clk_list_cnt = 69, + .soc_dev_clk_data = soc_dev_clk_data, + .soc_dev_clk_data_cnt = 69, +}; diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c new file mode 100644 index 0000000000..e140454c1e --- /dev/null +++ b/arch/arm/mach-k3/j721e/dev-data.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * J721E specific device platform data + * + * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ + */ +#include "k3-dev.h" + +static struct ti_psc soc_psc_list[] = { + [0] = PSC(0, 0x00400000), + [1] = PSC(1, 0x42000000), +}; + +static struct ti_pd soc_pd_list[] = { + [0] = PSC_PD(0, &soc_psc_list[0], NULL), + [1] = PSC_PD(14, &soc_psc_list[0], NULL), + [2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]), + [3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]), + [4] = PSC_PD(0, &soc_psc_list[1], NULL), +}; + +static struct ti_lpsc soc_lpsc_list[] = { + [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL), + [1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL), + [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]), + [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL), + [4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL), + [5] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL), + [6] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL), + [7] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[6]), + [8] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]), + [9] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL), + [10] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL), + [11] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL), + [12] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL), +}; + +static struct ti_dev soc_dev_list[] = { + PSC_DEV(30, &soc_lpsc_list[0]), + PSC_DEV(61, &soc_lpsc_list[0]), + PSC_DEV(146, &soc_lpsc_list[1]), + PSC_DEV(90, &soc_lpsc_list[2]), + PSC_DEV(47, &soc_lpsc_list[3]), + PSC_DEV(92, &soc_lpsc_list[4]), + PSC_DEV(91, &soc_lpsc_list[5]), + PSC_DEV(4, &soc_lpsc_list[6]), + PSC_DEV(202, &soc_lpsc_list[7]), + PSC_DEV(203, &soc_lpsc_list[8]), + PSC_DEV(103, &soc_lpsc_list[9]), + PSC_DEV(104, &soc_lpsc_list[9]), + PSC_DEV(154, &soc_lpsc_list[9]), + PSC_DEV(149, &soc_lpsc_list[9]), + PSC_DEV(197, &soc_lpsc_list[10]), + PSC_DEV(103, &soc_lpsc_list[11]), + PSC_DEV(104, &soc_lpsc_list[12]), +}; + +const struct ti_k3_pd_platdata j721e_pd_platdata = { + .psc = soc_psc_list, + .pd = soc_pd_list, + .lpsc = soc_lpsc_list, + .devs = soc_dev_list, + .num_psc = 2, + .num_pd = 5, + .num_lpsc = 13, + .num_devs = 17, +};

[PATCHv2,18/25] arm: mach-k3: Add platform data for j721e and j7200

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