From patchwork Wed Oct 28 10:34:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 1389225 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bp.renesas.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CLlMy4w6Rz9sVt for ; Wed, 28 Oct 2020 21:35:42 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 768CC824FC; Wed, 28 Oct 2020 11:35:01 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 80BBE824F6; Wed, 28 Oct 2020 11:34:53 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.5 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by phobos.denx.de (Postfix) with ESMTP id 59058823F4 for ; Wed, 28 Oct 2020 11:34:49 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=bp.renesas.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=biju.das.jz@bp.renesas.com X-IronPort-AV: E=Sophos;i="5.77,426,1596466800"; d="scan'208";a="61051264" Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie5.idc.renesas.com with ESMTP; 28 Oct 2020 19:34:47 +0900 Received: from localhost.localdomain (unknown [172.29.52.252]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id 2A08E4004950; Wed, 28 Oct 2020 19:34:44 +0900 (JST) From: Biju Das To: Nobuhiro Iwamatsu , Marek Vasut Cc: Biju Das , Lad Prabhakar , Adam Ford , Simon Glass , Masahiro Yamada , u-boot@lists.denx.de, Chris Paterson Subject: [PATCH 5/8] pinctrl: renesas: r8a7795: Optimize pinctrl image size for R8A774E1 Date: Wed, 28 Oct 2020 10:34:25 +0000 Message-Id: <20201028103429.3051-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201028103429.3051-1-biju.das.jz@bp.renesas.com> References: <20201028103429.3051-1-biju.das.jz@bp.renesas.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This driver supports both RZ/G2H and R-Car H3 SoCs. Optimize pinctrl image size for RZ/G2H, when support for R-Car H3 (R8A7795) is not enabled Based on the similar patch on Linux. Signed-off-by: Biju Das --- drivers/pinctrl/renesas/pfc-r8a7795.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index b787c4883a..898f837950 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -1836,6 +1836,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2050,6 +2051,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -4168,7 +4170,9 @@ static const unsigned int vin5_clk_mux[] = { static const struct { struct sh_pfc_pin_group common[320]; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 struct sh_pfc_pin_group automotive[30]; +#endif } pinmux_groups = { .common = { SH_PFC_PIN_GROUP(audio_clk_a_a), @@ -4492,6 +4496,7 @@ static const struct { SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, +#ifdef CONFIG_PINCTRL_PFC_R8A7795 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4524,7 +4529,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), } - +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ }; static const char * const audio_clk_groups[] = { @@ -4583,6 +4588,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4624,6 +4630,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ static const char * const du_groups[] = { "du_rgb666", @@ -5050,7 +5057,9 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[53]; +#ifdef CONFIG_PINCTRL_PFC_R8A7795 struct sh_pfc_function automotive[4]; +#endif } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), @@ -5107,13 +5116,14 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, +#ifdef CONFIG_PINCTRL_PFC_R8A7795 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), } - +#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = {