From patchwork Sun Oct 25 12:34:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1387188 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=UiVtvBIH; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CJy9r4Gsxz9sTD for ; Sun, 25 Oct 2020 23:35:44 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EFE528244A; Sun, 25 Oct 2020 13:35:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="UiVtvBIH"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 780EC8249C; Sun, 25 Oct 2020 13:35:08 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM,SPF_HELO_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-34.italiaonline.it [213.209.10.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 21E0E82474 for ; Sun, 25 Oct 2020 13:35:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([79.31.32.113]) by smtp-34.iol.local with ESMTPA id WfEbkQj5cmMFTWfEkkuGbV; Sun, 25 Oct 2020 13:35:03 +0100 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1603629303; bh=ezEpbWwmtaroE4k7s9s5oRflBtvQIbtmmCEpXeAgzgI=; h=From; b=UiVtvBIHij3ku8EBHVJOa7BlWFce/CnLehDW3RHBfUcQb8aLEYO73fIaZXUeI7Dz+ Ap2Fa3/2gRJj2zHOjXn8mYUdotphi6qyTGy+8kkN4I6nzBpO9RSqiljB0O68gFUH5I ViI/zA476IZVWAws7UgmYJHh3dILts9wHet16fYwAHp3aB923CwQ0/WAgZxJ19uMAg kFPWdKZG/Cj0e/YB3ZkmZGwmIduUhSjcLSDTl7RQ+Qwy3DxJYMvJwaOmJ8oQ6gdrLD PcBb2YmOoYKaYhszh+MGAX5UARmAnnZHB9oOTGdpVMREtl/RhExBcP1OjxYggK84iJ Uw39vnSCDZR7Q== X-CNFS-Analysis: v=2.4 cv=KetsDSUD c=1 sm=1 tr=0 ts=5f9570f7 a=9myQFBeCGQ66/mXSe6vdPA==:117 a=9myQFBeCGQ66/mXSe6vdPA==:17 a=dG0MHElxdOkkJmlQIB4A:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Dario Binacchi , Bharat Gooty , Lokesh Vutla , Masahiro Yamada , Rayagonda Kokatanur Subject: [PATCH v5 03/27] bus: ti: add minimal sysc interconnect target driver Date: Sun, 25 Oct 2020 13:34:26 +0100 Message-Id: <20201025123451.17579-4-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201025123451.17579-1-dariobin@libero.it> References: <20201025123451.17579-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfJCUzXV1sjs/6F+H4Byddytfi+f7UI1hwIcezxHQWLt5VEa9/KoxBdkpYMbCqKrOnTzlaB8hr2mLFxVyiM3dSqr+LTEZckPfE3fs2tG9UNKpCGvulIdu OYh+EvGQOjwXtuuzHPC+NzUCogfRgf5o3STEuFnaJCloupFsQ9JEd5neipa6wtDyob2XEf7ZwUt6DHe6onoZWEHv0Mv2BeBOyjxXHAQjdlXr3n5b+3oeSo8o YXnbqevqbYyG3lPBCjWIjTvqlcWjTfvo/2E7ZxbnYa2N5zfq/d7NKpK9I707jqZuHXNsFkEtJh5flwH/Xp7zJxmCLImYmVQSrngsrc2vumF/6cXz9Rxz+eaC jZQNslrNcPuGtYOYaKWHKY2cxbcaWdyAyZrhmkukOCKYxQv14HV7sK99l/q4b8CR/y4mHTiN X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean We can handle the sysc interconnect target module in a generic way for many TI SoCs. Initially let's just enable domain clocks before the children are probed. The code is loosely based on the drivers/bus/ti-sysc.c of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/bus/ti-sysc.txt Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Include device_compat.h header for dev_xxx macros. arch/arm/Kconfig | 1 + drivers/bus/Kconfig | 7 ++ drivers/bus/Makefile | 1 + drivers/bus/ti-sysc.c | 166 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+) create mode 100644 drivers/bus/ti-sysc.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80f09601e4..7c9e7b3d2e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -799,6 +799,7 @@ config ARCH_OMAP2PLUS select SPL_BOARD_INIT if SPL select SPL_STACK_R if SPL select SUPPORT_SPL + select TI_SYSC imply FIT config ARCH_MESON diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 07a33c6287..733bec5a56 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -5,6 +5,13 @@ menu "Bus devices" +config TI_SYSC + bool "TI sysc interconnect target module driver" + depends on ARCH_OMAP2PLUS + help + Generic driver for Texas Instruments interconnect target module + found on many TI SoCs. + config UNIPHIER_SYSTEM_BUS bool "UniPhier System Bus driver" depends on ARCH_UNIPHIER diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 0b97fc1f8b..875bb4ed42 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -3,4 +3,5 @@ # Makefile for the bus drivers. # +obj-$(CONFIG_TI_SYSC) += ti-sysc.o obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c new file mode 100644 index 0000000000..65974a70a6 --- /dev/null +++ b/drivers/bus/ti-sysc.c @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Texas Instruments sysc interconnect target driver + * + * Copyright (C) 2020 Dario Binacchi + */ + +#include +#include +#include +#include + +enum ti_sysc_clocks { + TI_SYSC_FCK, + TI_SYSC_ICK, + TI_SYSC_MAX_CLOCKS, +}; + +static const char *const clock_names[] = {"fck", "ick"}; + +struct ti_sysc_priv { + int clocks_count; + struct clk clocks[TI_SYSC_MAX_CLOCKS]; +}; + +static const struct udevice_id ti_sysc_ids[] = { + {.compatible = "ti,sysc-omap2"}, + {.compatible = "ti,sysc-omap4"}, + {.compatible = "ti,sysc-omap4-simple"}, + {.compatible = "ti,sysc-omap3430-sr"}, + {.compatible = "ti,sysc-omap3630-sr"}, + {.compatible = "ti,sysc-omap4-sr"}, + {.compatible = "ti,sysc-omap3-sham"}, + {.compatible = "ti,sysc-omap-aes"}, + {.compatible = "ti,sysc-mcasp"}, + {.compatible = "ti,sysc-usb-host-fs"}, + {} +}; + +static int ti_sysc_get_one_clock(struct udevice *dev, enum ti_sysc_clocks index) +{ + struct ti_sysc_priv *priv = dev_get_priv(dev); + const char *name; + int err; + + switch (index) { + case TI_SYSC_FCK: + break; + case TI_SYSC_ICK: + break; + default: + return -EINVAL; + } + + name = clock_names[index]; + + err = clk_get_by_name(dev, name, &priv->clocks[index]); + if (err) { + if (err == -ENODATA) + return 0; + + dev_err(dev, "failed to get %s clock\n", name); + return err; + } + + return 0; +} + +static int ti_sysc_put_clocks(struct udevice *dev) +{ + struct ti_sysc_priv *priv = dev_get_priv(dev); + int err; + + err = clk_release_all(priv->clocks, priv->clocks_count); + if (err) + dev_err(dev, "failed to release all clocks\n"); + + return err; +} + +static int ti_sysc_get_clocks(struct udevice *dev) +{ + struct ti_sysc_priv *priv = dev_get_priv(dev); + int i, err; + + for (i = 0; i < TI_SYSC_MAX_CLOCKS; i++) { + err = ti_sysc_get_one_clock(dev, i); + if (!err) + priv->clocks_count++; + else if (err != -ENOENT) + return err; + } + + return 0; +} + +static int ti_sysc_child_post_remove(struct udevice *dev) +{ + struct ti_sysc_priv *priv = dev_get_priv(dev->parent); + int i, err; + + for (i = 0; i < priv->clocks_count; i++) { + err = clk_disable(&priv->clocks[i]); + if (err) { + dev_err(dev->parent, "failed to disable %s clock\n", + clock_names[i]); + return err; + } + } + + return 0; +} + +static int ti_sysc_child_pre_probe(struct udevice *dev) +{ + struct ti_sysc_priv *priv = dev_get_priv(dev->parent); + int i, err; + + for (i = 0; i < priv->clocks_count; i++) { + err = clk_enable(&priv->clocks[i]); + if (err) { + dev_err(dev->parent, "failed to enable %s clock\n", + clock_names[i]); + return err; + } + } + + return 0; +} + +static int ti_sysc_remove(struct udevice *dev) +{ + return ti_sysc_put_clocks(dev); +} + +static int ti_sysc_probe(struct udevice *dev) +{ + int err; + + err = ti_sysc_get_clocks(dev); + if (err) + goto clocks_err; + + return 0; + +clocks_err: + ti_sysc_put_clocks(dev); + return err; +} + +UCLASS_DRIVER(ti_sysc) = { + .id = UCLASS_SIMPLE_BUS, + .name = "ti_sysc", + .post_bind = dm_scan_fdt_dev +}; + +U_BOOT_DRIVER(ti_sysc) = { + .name = "ti_sysc", + .id = UCLASS_SIMPLE_BUS, + .of_match = ti_sysc_ids, + .probe = ti_sysc_probe, + .remove = ti_sysc_remove, + .child_pre_probe = ti_sysc_child_pre_probe, + .child_post_remove = ti_sysc_child_post_remove, + .priv_auto_alloc_size = sizeof(struct ti_sysc_priv) +};