From patchwork Mon Oct 19 16:46:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 1384411 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.a=rsa-sha256 header.s=s2014 header.b=A7o1GnRK; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CFN6r09hFz9sS8 for ; Tue, 20 Oct 2020 03:50:43 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BC06C82444; Mon, 19 Oct 2020 18:49:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=libero.it header.i=@libero.it header.b="A7o1GnRK"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 26056823E5; Mon, 19 Oct 2020 18:49:12 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.7 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_SPF_HELO,FREEMAIL_FROM, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from libero.it (smtp-34-i2.italiaonline.it [213.209.12.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C36A282361 for ; Mon, 19 Oct 2020 18:49:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=libero.it Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=dariobin@libero.it Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([79.31.32.113]) by smtp-34.iol.local with ESMTPA id UYJRkIAvnmMFTUYLNkHdvn; Mon, 19 Oct 2020 18:49:09 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2014; t=1603126149; bh=tpMi8JKAsyWDpg1dSprSRKpGuKvOFfy78lyHxOyr1Z4=; h=From; b=A7o1GnRKHEkBOQevvp2Ai5vuje7UwRGsjfZtW9D2AADHxkMif36Baxvh43ptOGoZK nWeVUhBWjSHWN2vIETZqFfAHKgkqi0oDdl88fbPy3lkAVMcdXGEfTwEXZUXJ43OxvM Oo9e73dzm3sV+oLKNcypH7xyDlmR+Sy/MTIqRolDxKA8An3rD1Ca284OevzmA6h+k+ H2u+DLPf6xtoeyLN6in+IzQrnoYevIwxbsKp10FhmeXfgwHMB87OLi1Akhimih/Q+G +ZRzZys+JLpyc6iy9PBn51voD9BhFKRi+HFKf89zUK7dqN1QiRWR78ghur1nv3EItN jewkfKEaI/wrQ== X-CNFS-Analysis: v=2.4 cv=KetsDSUD c=1 sm=1 tr=0 ts=5f8dc385 a=9myQFBeCGQ66/mXSe6vdPA==:117 a=9myQFBeCGQ66/mXSe6vdPA==:17 a=m0E8M2FGYu1ttQaSf5kA:9 From: Dario Binacchi To: u-boot@lists.denx.de Cc: Dario Binacchi , Lokesh Vutla , Lukasz Majewski Subject: [PATCH v4 10/27] clk: ti: add gate clock driver Date: Mon, 19 Oct 2020 18:46:41 +0200 Message-Id: <20201019164658.13749-11-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201019164658.13749-1-dariobin@libero.it> References: <20201019164658.13749-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfGJPjO16x+otp2o1ip/Nle6Tw68Fam0A2BmUz+U3AWnZWsX3x+mQvLi2g+fYdPrCM0RJoi8NuVRvX3aFVq8QSJTECBOBSjGleBfDrQDd13B2zHJTkv60 VwRD0nmz1Yi1wA116FV0bdVlVLz4lCZWz5vTouaINPTW7AQgA5hSBFfXdT77nDGcQ4lbseCoQEbGbWg8NnT+xzWwC+go2PKlBwR9a6xbdUV4McmKWqb3AIqc sdHLT6zAXfIJH0/GeQyr8SCUsal4MFNEO0s51JqpHYrwxDHv/NC6yRo+J9I0//UZxT2klCGyp3PefhPfF+EBLQ== X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The patch adds support for TI gate clock binding. The code is based on the drivers/clk/ti/gate.c driver of the Linux kernel version 5.9-rc7. For DT binding details see: - Documentation/devicetree/bindings/clock/ti/gate.txt Signed-off-by: Dario Binacchi --- Changes in v4: - Include device_compat.h header for dev_xxx macros. Changes in v3: - Remove doc/device-tree-bindings/clock/gpio-gate-clock.txt. - Remove doc/device-tree-bindings/clock/ti,clockdomain.txt. - Remove doc/device-tree-bindings/clock/ti,gate.txt. - Add to commit message the references to linux kernel dt binding documentation. drivers/clk/Kconfig | 6 +++ drivers/clk/Makefile | 1 + drivers/clk/clk-ti-gate.c | 93 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+) create mode 100644 drivers/clk/clk-ti-gate.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index bc6bb57904..480ffc7d9c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -111,6 +111,12 @@ config CLK_TI_DIVIDER help This enables the divider clock driver support on TI's SoCs. +config CLK_TI_GATE + bool "TI gate clock driver" + depends on CLK && OF_CONTROL + help + This enables the gate clock driver support on TI's SoCs. + config CLK_TI_MUX bool "TI mux clock driver" depends on CLK && OF_CONTROL && CLK_CCF diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index ee218aff08..809672e92e 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o obj-$(CONFIG_STM32H7) += clk_stm32h7.o obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-ti-am3-dpll.o clk-ti-am3-dpll-x2.o obj-$(CONFIG_CLK_TI_DIVIDER) += clk-ti-divider.o +obj-$(CONFIG_CLK_TI_GATE) += clk-ti-gate.o obj-$(CONFIG_CLK_TI_MUX) += clk-ti-mux.o obj-$(CONFIG_CLK_TI_SCI) += clk-ti-sci.o obj-$(CONFIG_CLK_VERSAL) += clk_versal.o diff --git a/drivers/clk/clk-ti-gate.c b/drivers/clk/clk-ti-gate.c new file mode 100644 index 0000000000..6c5432c823 --- /dev/null +++ b/drivers/clk/clk-ti-gate.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * TI gate clock support + * + * Copyright (C) 2020 Dario Binacchi + * + * Loosely based on Linux kernel drivers/clk/ti/gate.c + */ + +#include +#include +#include +#include +#include +#include + +struct clk_ti_gate_priv { + fdt_addr_t reg; + u8 enable_bit; + u32 flags; + bool invert_enable; +}; + +static int clk_ti_gate_disable(struct clk *clk) +{ + struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev); + u32 v; + + v = readl(priv->reg); + if (priv->invert_enable) + v |= (1 << priv->enable_bit); + else + v &= ~(1 << priv->enable_bit); + + writel(v, priv->reg); + /* No OCP barrier needed here since it is a disable operation */ + return 0; +} + +static int clk_ti_gate_enable(struct clk *clk) +{ + struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev); + u32 v; + + v = readl(priv->reg); + if (priv->invert_enable) + v &= ~(1 << priv->enable_bit); + else + v |= (1 << priv->enable_bit); + + writel(v, priv->reg); + /* OCP barrier */ + v = readl(priv->reg); + return 0; +} + +static int clk_ti_gate_ofdata_to_platdata(struct udevice *dev) +{ + struct clk_ti_gate_priv *priv = dev_get_priv(dev); + + priv->reg = dev_read_addr(dev); + if (priv->reg == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get control register\n"); + return -EINVAL; + } + + dev_dbg(dev, "reg=0x%08lx\n", priv->reg); + priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0); + if (dev_read_bool(dev, "ti,set-rate-parent")) + priv->flags |= CLK_SET_RATE_PARENT; + + priv->invert_enable = dev_read_bool(dev, "ti,set-bit-to-disable"); + return 0; +} + +static struct clk_ops clk_ti_gate_ops = { + .enable = clk_ti_gate_enable, + .disable = clk_ti_gate_disable, +}; + +static const struct udevice_id clk_ti_gate_of_match[] = { + { .compatible = "ti,gate-clock" }, + { }, +}; + +U_BOOT_DRIVER(clk_ti_gate) = { + .name = "ti_gate_clock", + .id = UCLASS_CLK, + .of_match = clk_ti_gate_of_match, + .ofdata_to_platdata = clk_ti_gate_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct clk_ti_gate_priv), + .ops = &clk_ti_gate_ops, +};