From patchwork Fri Oct 16 14:23:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmarao Begari X-Patchwork-Id: 1383384 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.a=rsa-sha256 header.s=mchp header.b=vOXbsltV; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CCT306R5Lz9sTD for ; Sat, 17 Oct 2020 01:25:48 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A170D824EE; Fri, 16 Oct 2020 16:24:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=microchip.com header.i=@microchip.com header.b="vOXbsltV"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0F9F0824E7; Fri, 16 Oct 2020 16:24:33 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 06455824CD for ; Fri, 16 Oct 2020 16:24:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=microchip.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=Padmarao.Begari@microchip.com DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1602858269; x=1634394269; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=TJmGJ3+GYCafZZhu838n/C5xvz64k1Hj+y9cpyvO1BI=; b=vOXbsltVjwmCoOducazhd2hL93dZBLRO3Kl4Na2FEFQdFZTiQcH0BYQy gNVtyp/dUlr8dlQfiRFF9zqAed+ISlJX5XP4bRztXdtTDDP0Ae3iJfE3r 3oc0Zyh6Xu/h2PD7XN5DE72Ibqm9zEUfSA+KKjjvp+sCyfvARw1gdgcwU GzeQhY4/A4LzhtN2fqP9awswXd5ti638FDu00B93BH8tPiwD2i+X1fveI EeJk7Heyg8BWmdbq5wzWwjqy9mm8D2aHB+2lM674r8w/OnGRsACo6O2j7 5PQh9xjVOnQNV8kXQJ/bqDsBSgD71lpwkvPVI6BfR2TT0kB1Oqhjgm2JQ Q==; IronPort-SDR: SKupg7XrUjq/cmo9F5K8lVCsQPpG6xqCcAW3zWrw0/P+9VUcDUnoyuo9JVlm1I2sFP3Ad+xLcV trKUXRm6xYZy+M+0YCE/R7y+fRsyc0qhz4ZGe1n0G3Vbk8s3AzJdPMFELuuOxOjYIZyji6zX/q okFxT/LM3ORfDq63lFIY/9RtUviKyM5qnGgFLkjwgkr/p2eIoxBjFoG315Uohmjr+JADFB5YHQ ngUjqGRAktZ15uwfMoOvcIZUAUvhg1GJ4HWZ9w+YscXaOrXY/e/H6P56wl7seyKwVNgAHmSgZf EEQ= X-IronPort-AV: E=Sophos;i="5.77,383,1596524400"; d="scan'208";a="95634032" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Oct 2020 07:24:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Fri, 16 Oct 2020 07:24:28 -0700 Received: from ryzen.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.1979.3 via Frontend Transport; Fri, 16 Oct 2020 07:24:25 -0700 From: To: , , , , , , CC: , , , , , Padmarao Begari Subject: [PATCH v1 7/8] clk: Add Microchip PolarFire SoC clock driver Date: Fri, 16 Oct 2020 15:23:14 +0100 Message-ID: <20201016142315.30289-8-padmarao.begari@microchip.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201016142315.30289-1-padmarao.begari@microchip.com> References: <20201016142315.30289-1-padmarao.begari@microchip.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Padmarao Begari Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile | 1 + drivers/clk/microchip/clk_pfsoc.c | 120 ++++++++++++++++ drivers/clk/microchip/clk_pfsoc.h | 19 +++ drivers/clk/microchip/clk_pfsoc_cfg.c | 135 ++++++++++++++++++ drivers/clk/microchip/clk_pfsoc_periph.c | 171 +++++++++++++++++++++++ 8 files changed, 453 insertions(+) create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/clk_pfsoc.c create mode 100644 drivers/clk/microchip/clk_pfsoc.h create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4dfbad7986..1161fe7b5a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/imx/Kconfig" source "drivers/clk/kendryte/Kconfig" source "drivers/clk/meson/Kconfig" +source "drivers/clk/microchip/Kconfig" source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d1e295ac7c..bd8a6eed88 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_K210) += kendryte/ +obj-$(CONFIG_CLK_MPFS) += microchip/ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig new file mode 100644 index 0000000000..b70241559d --- /dev/null +++ b/drivers/clk/microchip/Kconfig @@ -0,0 +1,5 @@ +config CLK_MPFS + bool "Clock support for Microchip PolarFire SoC" + depends on CLK && CLK_CCF + help + This enables support clock driver for Microchip PolarFire SoC platform. diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile new file mode 100644 index 0000000000..c7f5ad21ae --- /dev/null +++ b/drivers/clk/microchip/Makefile @@ -0,0 +1 @@ +obj-y += clk_pfsoc.o clk_pfsoc_cfg.o clk_pfsoc_periph.o diff --git a/drivers/clk/microchip/clk_pfsoc.c b/drivers/clk/microchip/clk_pfsoc.c new file mode 100644 index 0000000000..6c7f89f25c --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk_pfsoc.h" + +/* All methods are delegated to CCF clocks */ + +static ulong pfsoc_clk_get_rate(struct clk *clk) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_get_rate(c); +} + +static ulong pfsoc_clk_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return clk_set_rate(c, rate); +} + +static int pfsoc_clk_set_parent(struct clk *clk, struct clk *parent) +{ + struct clk *c, *p; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + + err = clk_get_by_id(parent->id, &p); + if (err) + return err; + + return clk_set_parent(c, p); +} + +static int pfsoc_clk_endisable(struct clk *clk, bool enable) +{ + struct clk *c; + int err = clk_get_by_id(clk->id, &c); + + if (err) + return err; + return enable ? clk_enable(c) : clk_disable(c); +} + +static int pfsoc_clk_enable(struct clk *clk) +{ + return pfsoc_clk_endisable(clk, true); +} + +static int pfsoc_clk_disable(struct clk *clk) +{ + return pfsoc_clk_endisable(clk, false); +} + +static int pfsoc_clk_probe(struct udevice *dev) +{ + int ret; + void __iomem *base; + u32 clk_rate; + struct clk *clk; + const char *parent_clk_name; + + base = dev_read_addr_ptr(dev); + if (!base) + return -ENODEV; + clk = kzalloc(sizeof(*clk), GFP_KERNEL); + if (!clk) + return -ENOMEM; + + ret = clk_get_by_index(dev, 0, clk); + if (ret) + return ret; + dev_read_u32(clk->dev, "clock-frequency", &clk_rate); + parent_clk_name = clk->dev->name; + ret = pfsoc_clk_register_cfgs(base, clk_rate, parent_clk_name); + ret = pfsoc_clk_register_periphs(base, clk_rate, "clk_ahb"); + return ret; +} + +static const struct clk_ops pfsoc_clk_ops = { + .set_rate = pfsoc_clk_set_rate, + .get_rate = pfsoc_clk_get_rate, + .set_parent = pfsoc_clk_set_parent, + .enable = pfsoc_clk_enable, + .disable = pfsoc_clk_disable, +}; + +static const struct udevice_id pfsoc_of_match[] = { + { .compatible = "microchip,pfsoc-clkcfg" }, + { } +}; + +U_BOOT_DRIVER(pfsoc_clk) = { + .name = "pfsoc_clk", + .id = UCLASS_CLK, + .of_match = pfsoc_of_match, + .ops = &pfsoc_clk_ops, + .probe = pfsoc_clk_probe, +}; diff --git a/drivers/clk/microchip/clk_pfsoc.h b/drivers/clk/microchip/clk_pfsoc.h new file mode 100644 index 0000000000..3058b83f0d --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#ifndef __MICROCHIP_PFSOC_CLK_H +#define __MICROCHIP_PFSOC_CLK_H + +#include + +int pfsoc_clk_register_cfgs(void __iomem *base, u32 clk_rate, + const char *parent_name); +int pfsoc_clk_register_periphs(void __iomem *base, u32 clk_rate, + const char *parent_name); +int divider_get_val(unsigned long rate, unsigned long parent_rate, + const struct clk_div_table *table, + u8 width, unsigned long flags); + +#endif /* __MICROCHIP_PFSOC_CLK_H */ diff --git a/drivers/clk/microchip/clk_pfsoc_cfg.c b/drivers/clk/microchip/clk_pfsoc_cfg.c new file mode 100644 index 0000000000..a11def48d2 --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc_cfg.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk_pfsoc.h" + +#define PFSOC_CFG_CLOCK "pfsoc_cfg_clock" + +#define REG_CLOCK_CONFIG_CR 0x08 + +static const struct clk_div_table pfsoc_div_cpu_axi_table[] = { + { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, + { 0, 0 } +}; + +static const struct clk_div_table pfsoc_div_ahb_table[] = { + { 1, 2 }, { 2, 4}, { 3, 8 }, + { 0, 0 } +}; + +struct pfsoc_cfg_clock { + unsigned int id; + const char *name; + u8 shift; + u8 width; + const struct clk_div_table *table; + unsigned long flags; +}; + +struct pfsoc_cfg_hw_clock { + struct pfsoc_cfg_clock cfg; + void __iomem *sys_base; + u32 prate; + struct clk hw; +}; + +#define to_pfsoc_cfg_clk(_hw) container_of(_hw, struct pfsoc_cfg_hw_clock, hw) + +static unsigned long pfsoc_cfg_clk_recalc_rate(struct clk *hw) +{ + struct pfsoc_cfg_hw_clock *cfg_hw = to_pfsoc_cfg_clk(hw); + struct pfsoc_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + unsigned long rate; + u32 val; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift; + val &= clk_div_mask(cfg->width); + rate = cfg_hw->prate / (1u << val); + hw->rate = rate; + + return rate; +} + +static ulong pfsoc_cfg_clk_set_rate(struct clk *hw, ulong rate) +{ + struct pfsoc_cfg_hw_clock *cfg_hw = to_pfsoc_cfg_clk(hw); + struct pfsoc_cfg_clock *cfg = &cfg_hw->cfg; + void __iomem *base_addr = cfg_hw->sys_base; + u32 val; + int divider_setting; + + divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags); + + if (divider_setting < 0) + return divider_setting; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR); + val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift); + val |= divider_setting << cfg->shift; + writel(val, base_addr + REG_CLOCK_CONFIG_CR); + + return 0; +} + +#define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \ + .cfg.id = _id, \ + .cfg.name = _name, \ + .cfg.shift = _shift, \ + .cfg.width = _width, \ + .cfg.table = _table, \ + .cfg.flags = _flags, \ + } + +static struct pfsoc_cfg_hw_clock pfsoc_cfg_clks[] = { + CLK_CFG(CLK_CPU, "clk_cpu", 0, 2, pfsoc_div_cpu_axi_table, 0), + CLK_CFG(CLK_AXI, "clk_axi", 2, 2, pfsoc_div_cpu_axi_table, 0), + CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, pfsoc_div_ahb_table, 0), +}; + +int pfsoc_clk_register_cfgs(void __iomem *base, u32 clk_rate, + const char *parent_name) +{ + int ret; + int i, id, num_clks; + const char *name; + struct clk *hw; + + num_clks = ARRAY_SIZE(pfsoc_cfg_clks); + + for (i = 0; i < num_clks; i++) { + hw = &pfsoc_cfg_clks[i].hw; + pfsoc_cfg_clks[i].sys_base = base; + pfsoc_cfg_clks[i].prate = clk_rate; + name = pfsoc_cfg_clks[i].cfg.name; + ret = clk_register(hw, PFSOC_CFG_CLOCK, name, parent_name); + if (ret) + ERR_PTR(ret); + id = pfsoc_cfg_clks[i].cfg.id; + clk_dm(id, hw); + } + return 0; +} + +const struct clk_ops pfsoc_cfg_clk_ops = { + .set_rate = pfsoc_cfg_clk_set_rate, + .get_rate = pfsoc_cfg_clk_recalc_rate, +}; + +U_BOOT_DRIVER(pfsoc_cfg_clock) = { + .name = PFSOC_CFG_CLOCK, + .id = UCLASS_CLK, + .ops = &pfsoc_cfg_clk_ops, +}; diff --git a/drivers/clk/microchip/clk_pfsoc_periph.c b/drivers/clk/microchip/clk_pfsoc_periph.c new file mode 100644 index 0000000000..4dcab65eb2 --- /dev/null +++ b/drivers/clk/microchip/clk_pfsoc_periph.c @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk_pfsoc.h" + +#define PFSOC_PERIPH_CLOCK "pfsoc_periph_clock" + +#define REG_CLOCK_CONFIG_CR 0x08 +#define REG_SUBBLK_CLOCK_CR 0x84 +#define REG_SUBBLK_RESET_CR 0x88 + +#define CFG_CPU_SHIFT 0x0 +#define CFG_AXI_SHIFT 0x2 +#define CFG_AHB_SHIFT 0x4 +#define CFG_WIDTH 0x2 + +struct pfsoc_periph_clock { + unsigned int id; + const char *name; + u8 shift; + unsigned long flags; +}; + +struct pfsoc_periph_hw_clock { + struct pfsoc_periph_clock periph; + void __iomem *sys_base; + u32 prate; + struct clk hw; +}; + +#define to_pfsoc_periph_clk(_hw) container_of(_hw, struct pfsoc_periph_hw_clock, hw) + +static int pfsoc_periph_clk_enable(struct clk *hw) +{ + struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw); + struct pfsoc_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + + if (periph->flags != CLK_IS_CRITICAL) { + reg = readl(base_addr + REG_SUBBLK_RESET_CR); + val = reg & ~(1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg | (1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + } + + return 0; +} + +static int pfsoc_periph_clk_disable(struct clk *hw) +{ + struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw); + struct pfsoc_periph_clock *periph = &periph_hw->periph; + void __iomem *base_addr = periph_hw->sys_base; + u32 reg, val; + + if (periph->flags != CLK_IS_CRITICAL) { + reg = readl(base_addr + REG_SUBBLK_RESET_CR); + val = reg | (1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_RESET_CR); + + reg = readl(base_addr + REG_SUBBLK_CLOCK_CR); + val = reg & ~(1u << periph->shift); + writel(val, base_addr + REG_SUBBLK_CLOCK_CR); + } + + return 0; +} + +static unsigned long pfsoc_periph_clk_recalc_rate(struct clk *hw) +{ + struct pfsoc_periph_hw_clock *periph_hw = to_pfsoc_periph_clk(hw); + void __iomem *base_addr = periph_hw->sys_base; + u32 rate, val; + + val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> CFG_AHB_SHIFT; + val &= clk_div_mask(CFG_WIDTH); + rate = periph_hw->prate / (1u << val); + hw->rate = rate; + return rate; +} + +#define CLK_PERIPH(_id, _name, _shift, _flags) { \ + .periph.id = _id, \ + .periph.name = _name, \ + .periph.shift = _shift, \ + .periph.flags = _flags, \ + } + +static struct pfsoc_periph_hw_clock pfsoc_periph_clks[] = { + CLK_PERIPH(CLK_ENVM, "clk_periph_envm", 0, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", 1, 0), + CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", 2, 0), + CLK_PERIPH(CLK_MMC, "clk_periph_mmc", 3, 0), + CLK_PERIPH(CLK_TIMER, "clk_periph_timer", 4, 0), + CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", 5, 0), + CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", 6, 0), + CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", 7, 0), + CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", 8, 0), + CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", 9, 0), + CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", 10, 0), + CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", 11, 0), + CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", 12, 0), + CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", 13, 0), + CLK_PERIPH(CLK_CAN0, "clk_periph_can0", 14, 0), + CLK_PERIPH(CLK_CAN1, "clk_periph_can1", 15, 0), + CLK_PERIPH(CLK_USB, "clk_periph_usb", 16, 0), + CLK_PERIPH(CLK_RTC, "clk_periph_rtc", 18, 0), + CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", 19, 0), + CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", 20, 0), + CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", 21, 0), + CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", 22, 0), + CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", 23, CLK_IS_CRITICAL), + CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", 24, 0), + CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", 25, 0), + CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", 26, 0), + CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", 27, 0), + CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", 28, 0), + CLK_PERIPH(CLK_CFM, "clk_periph_cfm", 29, 0), +}; + +int pfsoc_clk_register_periphs(void __iomem *base, u32 clk_rate, + const char *parent_name) +{ + int ret; + int i, id, num_clks; + const char *name; + struct clk *hw; + + num_clks = ARRAY_SIZE(pfsoc_periph_clks); + for (i = 0; i < num_clks; i++) { + hw = &pfsoc_periph_clks[i].hw; + pfsoc_periph_clks[i].sys_base = base; + pfsoc_periph_clks[i].prate = clk_rate; + name = pfsoc_periph_clks[i].periph.name; + ret = clk_register(hw, PFSOC_PERIPH_CLOCK, name, parent_name); + if (ret) + ERR_PTR(ret); + id = pfsoc_periph_clks[i].periph.id; + clk_dm(id, hw); + } + + return 0; +} + +const struct clk_ops pfsoc_periph_clk_ops = { + .enable = pfsoc_periph_clk_enable, + .disable = pfsoc_periph_clk_disable, + .get_rate = pfsoc_periph_clk_recalc_rate, +}; + +U_BOOT_DRIVER(pfsoc_periph_clock) = { + .name = PFSOC_PERIPH_CLOCK, + .id = UCLASS_CLK, + .ops = &pfsoc_periph_clk_ops, +};