| Message ID | 20201016031332.21456-2-yangbo.lu@nxp.com |
|---|---|
| State | Superseded |
| Delegated to: | Peng Fan |
| Headers | show |
| Series | mmc: fsl_esdhc: fix up for eMMC HS400 | expand |
Dear Yangbo, On 10/16/20 12:13 PM, Yangbo Lu wrote: > The initial clock setting should be through sysctl register only, > while the mmc_set_clock() will call mmc_set_ios() introduce other > configurations like bus width, mode, and so on. > > Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung > --- > drivers/mmc/fsl_esdhc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c > index 642784e..68130ee 100644 > --- a/drivers/mmc/fsl_esdhc.c > +++ b/drivers/mmc/fsl_esdhc.c > @@ -715,7 +715,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) > esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); > > /* Set the initial clock speed */ > - mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); > + set_sysctl(priv, mmc, 400000); > > /* Disable the BRR and BWR bits in IRQSTAT */ > esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); >
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 642784e..68130ee 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -715,7 +715,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ - mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); + set_sysctl(priv, mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> --- drivers/mmc/fsl_esdhc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)