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[v3,09/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver

Message ID 20201015122955.10259-10-elly.siew.chin.lim@intel.com
State Superseded
Delegated to: Simon Goldschmidt
Headers show
Series Enable ARM Trusted Firmware for U-Boot | expand

Commit Message

Siew Chin Lim Oct. 15, 2020, 12:29 p.m. UTC 
From: Chee Hong Ang <chee.hong.ang@intel.com>

In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/reset_manager_s10.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

Comments

Ley Foon Tan Nov. 12, 2020, 11:03 a.m. UTC | #1 
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Sent: Thursday, October 15, 2020 8:30 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; See, Chin Liang <chin.liang.see@intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>; Simon Glass <sjg@chromium.org>; Ang,
> Chee Hong <chee.hong.ang@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [v3 09/16] arm: socfpga: soc64: Add ATF support for Reset Manager
> driver
> 
> From: Chee Hong Ang <chee.hong.ang@intel.com>
> 
> In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service
> provided by ATF to enable/disable the SOCFPGA bridges.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> ---
>  arch/arm/mach-socfpga/reset_manager_s10.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
> b/arch/arm/mach-socfpga/reset_manager_s10.c
> index 3746e6a60c..af8f2c0873 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> @@ -5,11 +5,14 @@
>   */
> 

Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 3746e6a60c..af8f2c0873 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@ 
  */
 
 #include <common.h>
+#include <hang.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/smc_api.h>
 #include <asm/arch/system_manager.h>
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 #include <linux/iopoll.h>
+#include <linux/intel-smc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +58,15 @@  void socfpga_per_reset_all(void)
 
 void socfpga_bridges_reset(int enable)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	u64 arg = enable;
+
+	int ret = invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0);
+	if (ret) {
+		printf("SMC call failed with error %d in %s.\n", ret, __func__);
+		return;
+	}
+#else
 	u32 reg;
 
 	if (enable) {
@@ -101,6 +113,7 @@  void socfpga_bridges_reset(int enable)
 		/* Disable NOC timeout */
 		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 	}
+#endif
 }
 
 /*