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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id t3sm12968651qtq.24.2020.10.12.11.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 11:15:07 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Heinrich Schuchardt , Rick Chen , Bin Meng , Sean Anderson , Damien Le Moal , Lukasz Majewski Subject: [PATCH v2 01/16] clk: k210: Fix PLLs not being enabled Date: Mon, 12 Oct 2020 14:13:30 -0400 Message-Id: <20201012181345.338661-2-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201012181345.338661-1-seanga2@gmail.com> References: <20201012181345.338661-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen --- (no changes since v1) drivers/clk/kendryte/pll.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index ab6d75d585..f198920113 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk) k210_pll_waitfor_lock(pll); reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; writel(reg, pll->reg); return 0; @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk) writel(reg, pll->reg); reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; writel(reg, pll->reg); return 0; }