From patchwork Tue Sep 29 18:52:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ralph Siemsen X-Patchwork-Id: 1373571 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=sq6sumYr; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C17mc0XGfz9sSC for ; Wed, 30 Sep 2020 04:52:32 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 221F58174F; Tue, 29 Sep 2020 20:52:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="sq6sumYr"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 71B9781996; Tue, 29 Sep 2020 20:52:27 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x844.google.com (mail-qt1-x844.google.com [IPv6:2607:f8b0:4864:20::844]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9ABAE808F1 for ; Tue, 29 Sep 2020 20:52:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ralph.siemsen@linaro.org Received: by mail-qt1-x844.google.com with SMTP id a4so4443034qth.0 for ; Tue, 29 Sep 2020 11:52:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=qymXYOtSCXQiY5a3GFFd/e3CZOyfn5BzXPwnfzqqxwo=; b=sq6sumYrsnXP03kXbx1dobnA+0LUEKWmqgSSoEx6qHPfnmMpBAGeYZYmIeqULQBEKi MH8mOTCXP1RsOdDs5ZLjuTXPtdqMzWmVQcBq2xpeOMVPrA3oYGzz7BA7xqFNa8ki+zC4 bs7VHAU03P62wHoW8OGotSlTbCB9KcZqco138z0rn7cSa9g9G2cB38UJf9SYIV7cvJY2 zIG8yRMBoD8Ix/jcNkCNvJFda7KzPsc16T94zoBLHCK2aoE00y1BYoAj8en9J9YgUm4e MRW3N+kkHee95JfjCnohI10ktyG6P2EOZw3IVLHhuV+qFM0sx8QsKbJBLMB9OGHhfIvO QXmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=qymXYOtSCXQiY5a3GFFd/e3CZOyfn5BzXPwnfzqqxwo=; b=tGkS8ACmulpGX1aTGPhkAJEydlFX5byjSnsVrW4RikXxipd3xaBFubMVJv8GERdKlI 7BOZivSAHcrzAbWQEDkViEOtmIeZ5yYEluoDtMkztqO9AwNw8Nl+vlz1Iz8VOpbc6u6Y RX6vGpX/u19GoTSvjjTEjiaQmvrSXSb3eoQ3XUEMnu9vH6xw+yK9d3GD8hC2Sll5PFv8 Me5LQ71Ams0zI+YCsOlA7W8bZiASKklLBSK87olPJ/C7seyGF5tOtOPicejLe0Mo96ge SNnXks9KwGrfsrKJO9sTL11ovoZxcxpxU/kMCY7zFM8RDicSix/YiWt+zcgTTcnkQail e6NA== X-Gm-Message-State: AOAM531oBN9r1gxt9k8u86xIt7mVBfKWd6SCQLRXc7kFKiMxvb8iayQF zBhMhMmhestzLk/x1QI/d7v/Nw== X-Google-Smtp-Source: ABdhPJyGyTRRH6XcxluZx56f0P62/vldqcfHNLLTdTHBOCWyTt8A3xAP2oTuZQ4dvVGeEqR9kx1WEg== X-Received: by 2002:ac8:5d43:: with SMTP id g3mr4917532qtx.295.1601405543434; Tue, 29 Sep 2020 11:52:23 -0700 (PDT) Received: from maple.netwinder.org (rfs.netwinder.org. [206.248.184.2]) by smtp.gmail.com with ESMTPSA id f24sm5370433qkk.136.2020.09.29.11.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2020 11:52:22 -0700 (PDT) From: Ralph Siemsen To: Ley Foon Tan Cc: Dinh Nguyen , Marek Vasut , Simon Goldschmidt , u-boot@lists.denx.de, Tom Rini , Ralph Siemsen Subject: [PATCH v1] arm: socfpga: fix Gen5 enable of EMAC via FPGA Date: Tue, 29 Sep 2020 14:52:05 -0400 Message-Id: <20200929145152.v1.1.I7900a579743ce0fc5fe382213612b5af29e3706f@changeid> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean An earlier conversion from struct to defines introduced two errors, both related to setup of EMAC routed via the FPGA. One of the offsets was incorrect, and the EMAC0/EMAC1 were swapped. The effect of this was rather odd: both ports could operate at gigabit, but one of them would fail to transmit when operating at 100Mbit. Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system manager from struct to defines") Signed-off-by: Ralph Siemsen Reviewed-by: Ley Foon Tan --- I reviewed the other #defines for gen5 and they seem correct. I have NOT checked the defines for Arria 10 or Stratix 10! arch/arm/mach-socfpga/include/mach/system_manager_gen5.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h index 90cb465d13..a63a4ee27d 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h @@ -26,9 +26,9 @@ void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #define SYSMGR_GEN5_ECCGRP_OCRAM 0x144 #define SYSMGR_GEN5_EMACIO 0x400 #define SYSMGR_GEN5_NAND_USEFPGA 0x6f0 -#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8 +#define SYSMGR_GEN5_RGMII1_USEFPGA 0x6f8 #define SYSMGR_GEN5_SDMMC_USEFPGA 0x708 -#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704 +#define SYSMGR_GEN5_RGMII0_USEFPGA 0x714 #define SYSMGR_GEN5_SPIM1_USEFPGA 0x730 #define SYSMGR_GEN5_SPIM0_USEFPGA 0x738