diff mbox series

[32/32] x86: fsp: Adjust calculations for MTRR range and DRAM top

Message ID 20200928042611.1696178-31-sjg@chromium.org
State New
Delegated to: Bin Meng
Headers show
Series x86: Allow Coral to boot into Chrome OS | expand

Commit Message

Simon Glass Sept. 28, 2020, 4:26 a.m. UTC
At present the top of available DRAM is the same as the top of the range
of the low-memory MTRR.

In fact, U-Boot is allowed to use memory up until the start of the FSP
reserved memory. Use that value for low_end, since it makes more memory
available.

Keep the same calculation as before for mtrr_top, i.e. the top of
reserved memory.

A side-effect of this change is that the E820 tables have a single entry
that extends from the bottom of the memory used by U-Boot to the bottom
of the FSP reserved memory. This includes the bloblist, if ACPI tables
are placed there.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/fsp/fsp_dram.c | 35 ++++++++++++++++++++++-------------
 1 file changed, 22 insertions(+), 13 deletions(-)

Comments

Bin Meng Oct. 16, 2020, 2:17 p.m. UTC | #1
On Mon, Sep 28, 2020 at 12:26 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present the top of available DRAM is the same as the top of the range
> of the low-memory MTRR.
>
> In fact, U-Boot is allowed to use memory up until the start of the FSP
> reserved memory. Use that value for low_end, since it makes more memory
> available.
>
> Keep the same calculation as before for mtrr_top, i.e. the top of
> reserved memory.
>
> A side-effect of this change is that the E820 tables have a single entry
> that extends from the bottom of the memory used by U-Boot to the bottom
> of the FSP reserved memory. This includes the bloblist, if ACPI tables
> are placed there.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/fsp/fsp_dram.c | 35 ++++++++++++++++++++++-------------
>  1 file changed, 22 insertions(+), 13 deletions(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index a76497d4e01..3ffd40ce747 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -41,8 +41,10 @@  int fsp_scan_for_ram_size(void)
 
 int dram_init_banksize(void)
 {
+	efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
 	const struct hob_header *hdr;
 	struct hob_res_desc *res_desc;
+	phys_addr_t mtrr_top;
 	phys_addr_t low_end;
 	uint bank;
 
@@ -54,35 +56,42 @@  int dram_init_banksize(void)
 		return 0;
 	}
 
-	low_end = 0;
+	low_end = 0;	/* top of low memory usable by U-Boot */
+	mtrr_top = 0;	/* top of low memory (even if reserved) */
 	for (bank = 1, hdr = gd->arch.hob_list;
 	     bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
 	     hdr = get_next_hob(hdr)) {
 		if (hdr->type != HOB_TYPE_RES_DESC)
 			continue;
 		res_desc = (struct hob_res_desc *)hdr;
+		if (!guidcmp(&res_desc->owner, &fsp))
+			low_end = res_desc->phys_start;
 		if (res_desc->type != RES_SYS_MEM &&
 		    res_desc->type != RES_MEM_RESERVED)
 			continue;
 		if (res_desc->phys_start < (1ULL << 32)) {
-			low_end = max(low_end,
-				      res_desc->phys_start + res_desc->len);
-			continue;
+			mtrr_top = max(mtrr_top,
+				       res_desc->phys_start + res_desc->len);
+		} else {
+			gd->bd->bi_dram[bank].start = res_desc->phys_start;
+			gd->bd->bi_dram[bank].size = res_desc->len;
+			mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
+					 res_desc->len);
+			log_debug("ram %llx %llx\n",
+				  gd->bd->bi_dram[bank].start,
+				  gd->bd->bi_dram[bank].size);
 		}
-
-		gd->bd->bi_dram[bank].start = res_desc->phys_start;
-		gd->bd->bi_dram[bank].size = res_desc->len;
-		mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
-				 res_desc->len);
-		log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
-			  gd->bd->bi_dram[bank].size);
 	}
 
 	/* Add the memory below 4GB */
 	gd->bd->bi_dram[0].start = 0;
 	gd->bd->bi_dram[0].size = low_end;
 
-	mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
+	/*
+	 * Set up an MTRR to the top of low, reserved memory. This is necessary
+	 * for graphics to run at full speed in U-Boot.
+	 */
+	mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
 
 	return 0;
 }
@@ -156,7 +165,7 @@  unsigned int install_e820_map(unsigned int max_entries,
 #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
 int handoff_arch_save(struct spl_handoff *ho)
 {
-	ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
+	ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
 	ho->arch.hob_list = gd->arch.hob_list;
 
 	return 0;