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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id k51sm2620579otc.46.2020.09.27.21.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Sep 2020 21:26:44 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Andy Shevchenko , Heinrich Schuchardt , Bernhard Messerklinger , Wolfgang Wallner , Walter Lozano , Simon Glass , Bin Meng , Michal Simek , Ovidiu Panait , Peng Fan , Reuben Dowle Subject: [PATCH 24/32] x86: Use CONFIG_CHROMEOS_VBOOT for verified boot Date: Sun, 27 Sep 2020 22:26:03 -0600 Message-Id: <20200928042611.1696178-23-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.681.g6f77f65b4e-goog In-Reply-To: <20200928042611.1696178-1-sjg@chromium.org> References: <20200928042611.1696178-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean At present CONFIG_CHROMEOS is used to determine whether verified boot is in use. The code to implement that is not in U-Boot mainline. However, it is useful to be able to boot a Chromebook in developer mode in U-Boot mainline without needing the verified boot code. To allow this, use CONFIG_CHROMEOS_VBOOT to indicate that verified boot should be used, and CONFIG_CHROMEOS to indicate that the board supports Chrome OS. That allows us to define CONFIG_CHROMEOS on coral. Signed-off-by: Simon Glass --- Kconfig | 8 ++++++++ arch/x86/dts/chromebook_coral.dts | 2 +- arch/x86/dts/chromebook_samus.dts | 2 +- arch/x86/include/asm/intel_gnvs.h | 3 --- arch/x86/lib/tpl.c | 2 +- configs/chromebook_coral_defconfig | 3 ++- 6 files changed, 13 insertions(+), 7 deletions(-) diff --git a/Kconfig b/Kconfig index 837b2f517ae..bd3bcb0d6f1 100644 --- a/Kconfig +++ b/Kconfig @@ -759,6 +759,14 @@ config ARCH_FIXUP_FDT_MEMORY used for booting OS with different memory setup where the part of the memory location should be used for different purpose. +config CHROMEOS + bool "Support booting Chrome OS" + help + Chrome OS requires U-Boot to set up a table indicating the boot mode + (e.g. Developer mode) and a few other things. Enable this if you are + booting on a Chromebook to avoid getting an error about an invalid + firmware ID. + endmenu # Boot images source "api/Kconfig" diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 92f70b13dd7..43f4b33da1b 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -9,7 +9,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_CHROMEOS_VBOOT #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-16mb-rw.dtsi" diff --git a/arch/x86/dts/chromebook_samus.dts b/arch/x86/dts/chromebook_samus.dts index 772ea5c91be..d8e04a66985 100644 --- a/arch/x86/dts/chromebook_samus.dts +++ b/arch/x86/dts/chromebook_samus.dts @@ -9,7 +9,7 @@ /include/ "rtc.dtsi" /include/ "tsc_timer.dtsi" -#ifdef CONFIG_CHROMEOS +#ifdef CONFIG_CHROMEOS_VBOOT #include "chromeos-x86.dtsi" #include "flashmap-x86-ro.dtsi" #include "flashmap-8mb-rw.dtsi" diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h index a2c17bf646f..3466c30bf72 100644 --- a/arch/x86/include/asm/intel_gnvs.h +++ b/arch/x86/include/asm/intel_gnvs.h @@ -85,9 +85,6 @@ struct __packed acpi_global_nvs { u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ #endif }; - -#ifdef CONFIG_CHROMEOS check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif #endif /* _INTEL_GNVS_H_ */ diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 6f7eb43a172..15b0212d190 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -75,7 +75,7 @@ void board_init_f_r(void) u32 spl_boot_device(void) { - return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT : + return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT : BOOT_DEVICE_SPI_MMAP; } diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index af0397ff1f4..827974f7fcf 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -2,9 +2,9 @@ CONFIG_X86=y CONFIG_SYS_TEXT_BASE=0x1110000 CONFIG_SYS_MALLOC_F_LEN=0x3d00 CONFIG_NR_DRAM_BANKS=8 +CONFIG_MAX_CPUS=8 CONFIG_SPL_DM_SPI=y CONFIG_SPL_TEXT_BASE=0xfef10000 -CONFIG_MAX_CPUS=8 CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000 CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000 CONFIG_DEBUG_UART_BOARD_INIT=y @@ -21,6 +21,7 @@ CONFIG_INTEL_CAR_CQOS=y CONFIG_X86_OFFSET_U_BOOT=0xffd00000 CONFIG_X86_OFFSET_SPL=0xffe80000 CONFIG_INTEL_GENERIC_WIFI=y +CONFIG_CHROMEOS=y CONFIG_BOOTSTAGE=y CONFIG_SPL_BOOTSTAGE=y CONFIG_TPL_BOOTSTAGE=y