diff mbox series

[12/32] x86: Move ROM_TABLE_ADDR into the C file

Message ID 20200928042611.1696178-11-sjg@chromium.org
State New
Delegated to: Bin Meng
Headers show
Series x86: Allow Coral to boot into Chrome OS | expand

Commit Message

Simon Glass Sept. 28, 2020, 4:25 a.m. UTC
At present this is defined in the header file, along with a few related
defines. The code that used to need this has been removed. Move it into
the C file instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/tables.h | 8 --------
 arch/x86/lib/tables.c         | 8 ++++++++
 2 files changed, 8 insertions(+), 8 deletions(-)

Comments

Bin Meng Oct. 16, 2020, 1:34 p.m. UTC | #1
Hi Simon,

On Mon, Sep 28, 2020 at 12:26 PM Simon Glass <sjg@chromium.org> wrote:
>
> At present this is defined in the header file, along with a few related
> defines. The code that used to need this has been removed. Move it into
> the C file instead.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/tables.h | 8 --------
>  arch/x86/lib/tables.c         | 8 ++++++++
>  2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
> index bf66e79018e..ff15949bd47 100644
> --- a/arch/x86/include/asm/tables.h
> +++ b/arch/x86/include/asm/tables.h
> @@ -8,14 +8,6 @@
>
>  #include <tables_csum.h>
>
> -#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR
> -#define ROM_TABLE_END  (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
> -
> -#define ROM_TABLE_ALIGN        1024

These macros are still referenced by arch/x86/lib/acpi.c. Am I missing
something?

> -
> -/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
> -#define CB_TABLE_ADDR  0x800
> -
>  /**
>   * table_compute_checksum() - Compute a table checksum
>   *
> diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
> index 7099866a78a..43b61a7aeac 100644
> --- a/arch/x86/lib/tables.c
> +++ b/arch/x86/lib/tables.c
> @@ -13,6 +13,14 @@
>  #include <asm/tables.h>
>  #include <asm/coreboot_tables.h>
>
> +#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR
> +#define ROM_TABLE_END  (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
> +
> +#define ROM_TABLE_ALIGN        1024
> +
> +/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
> +#define CB_TABLE_ADDR  0x800
> +
>  /**
>   * Function prototype to write a specific configuration table
>   *
> --

Regards,
Bin
diff mbox series

Patch

diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h
index bf66e79018e..ff15949bd47 100644
--- a/arch/x86/include/asm/tables.h
+++ b/arch/x86/include/asm/tables.h
@@ -8,14 +8,6 @@ 
 
 #include <tables_csum.h>
 
-#define ROM_TABLE_ADDR	CONFIG_ROM_TABLE_ADDR
-#define ROM_TABLE_END	(CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
-
-#define ROM_TABLE_ALIGN	1024
-
-/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
-#define CB_TABLE_ADDR	0x800
-
 /**
  * table_compute_checksum() - Compute a table checksum
  *
diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c
index 7099866a78a..43b61a7aeac 100644
--- a/arch/x86/lib/tables.c
+++ b/arch/x86/lib/tables.c
@@ -13,6 +13,14 @@ 
 #include <asm/tables.h>
 #include <asm/coreboot_tables.h>
 
+#define ROM_TABLE_ADDR	CONFIG_ROM_TABLE_ADDR
+#define ROM_TABLE_END	(CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1)
+
+#define ROM_TABLE_ALIGN	1024
+
+/* SeaBIOS expects coreboot tables at address range 0x0000-0x1000 */
+#define CB_TABLE_ADDR	0x800
+
 /**
  * Function prototype to write a specific configuration table
  *