diff mbox series

[v4,41/59] x86: cpu: Report address width from cpu_get_info()

Message ID 20200922124521.v4.41.I118f06c4ecc36bca1be6229e54e03511110a84a0@changeid
State Accepted
Commit aec7c1c565b0455a0523e8d486294843fd93bca9
Delegated to: Bin Meng
Headers show
Series dm: Add programatic generation of ACPI tables (part D) | expand

Commit Message

Simon Glass Sept. 22, 2020, 6:45 p.m. UTC
Add support for this new field in the common code used by most x86 CPU
drivers.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

(no changes since v1)

 arch/x86/cpu/i386/cpu.c         | 23 +++++++++++++++++++++++
 arch/x86/cpu/intel_common/cpu.c |  1 +
 arch/x86/cpu/x86_64/cpu.c       |  5 +++++
 arch/x86/include/asm/cpu.h      |  9 +++++++++
 4 files changed, 38 insertions(+)
diff mbox series

Patch

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index 8f342dd06e2..7517b756f43 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -34,6 +34,10 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define CPUID_FEATURE_PAE	BIT(6)
+#define CPUID_FEATURE_PSE36	BIT(17)
+#define CPUID_FEAURE_HTT	BIT(28)
+
 /*
  * Constructor for a conventional segment GDT (or LDT) entry
  * This is a macro so it can be used in initialisers
@@ -388,6 +392,25 @@  static void setup_identity(void)
 	}
 }
 
+static uint cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+int cpu_phys_address_size(void)
+{
+	if (!has_cpuid())
+		return 32;
+
+	if (cpu_cpuid_extended_level() >= 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+
+	return 32;
+}
+
 /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
 static void setup_pci_ram_top(void)
 {
diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c
index d8a3d60ae72..39aa0f63c65 100644
--- a/arch/x86/cpu/intel_common/cpu.c
+++ b/arch/x86/cpu/intel_common/cpu.c
@@ -127,6 +127,7 @@  int cpu_intel_get_info(struct cpu_info *info, int bclk)
 	info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
 	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
 		1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
+	info->address_width = cpu_phys_address_size();
 
 	return 0;
 }
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 1b4d3971b04..90a766c3c57 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -70,3 +70,8 @@  int x86_cpu_reinit_f(void)
 {
 	return 0;
 }
+
+int cpu_phys_address_size(void)
+{
+	return CONFIG_CPU_ADDR_BITS;
+}
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 21a05dab7de..5b001bbee21 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -288,4 +288,13 @@  u32 cpu_get_family_model(void);
  */
 u32 cpu_get_stepping(void);
 
+/**
+ * cpu_phys_address_size() - Get the physical address size in bits
+ *
+ * This is 32 for older CPUs but newer ones may support 36.
+ *
+ * @return address size (typically 32 or 36)
+ */
+int cpu_phys_address_size(void);
+
 #endif