diff mbox series

[v1,07/22] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h

Message ID 20200922094930.100855-8-elly.siew.chin.lim@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Diamond Mesa SoC support | expand

Commit Message

Siew Chin Lim Sept. 22, 2020, 9:49 a.m. UTC
No functionality change. In preparation for Stratix10 and
Agilex handoff function restructuring.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 46 +++++++++++-----------
 1 file changed, 24 insertions(+), 22 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 6c84abe324..dbd19f602c 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@ 
 /* SPDX-License-Identifier: GPL-2.0
  *
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2020 Intel Corporation <www.intel.com>
  *
  */
 
@@ -10,30 +10,32 @@ 
 /*
  * Offset for HW handoff from Quartus tools
  */
-#define SOC64_HANDOFF_BASE		0xFFE3F000
-#define SOC64_HANDOFF_MUX		(SOC64_HANDOFF_BASE + 0x10)
-#define SOC64_HANDOFF_IOCTL		(SOC64_HANDOFF_BASE + 0x1A0)
-#define SOC64_HANDOFF_FPGA		(SOC64_HANDOFF_BASE + 0x330)
-#define SOC64_HANDOFF_DELAY		(SOC64_HANDOFF_BASE + 0x3F0)
-#define SOC64_HANDOFF_CLOCK		(SOC64_HANDOFF_BASE + 0x580)
-#define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x610)
-#define SOC64_HANDOFF_MAGIC_MUX		0x504D5558
-#define SOC64_HANDOFF_MAGIC_IOCTL	0x494F4354
-#define SOC64_HANDOFF_MAGIC_FPGA	0x46504741
-#define SOC64_HANDOFF_MAGIC_DELAY	0x444C4159
-#define SOC64_HANDOFF_MAGIC_CLOCK	0x434C4B53
-#define SOC64_HANDOFF_MAGIC_MISC	0x4D495343
-#define SOC64_HANDOFF_OFFSET_LENGTH	0x4
-#define SOC64_HANDOFF_OFFSET_DATA	0x10
+/* HPS handoff */
+#define SOC64_HANDOFF_MAGIC_MUX			0x504D5558
+#define SOC64_HANDOFF_MAGIC_IOCTL		0x494F4354
+#define SOC64_HANDOFF_MAGIC_FPGA		0x46504741
+#define SOC64_HANDOFF_MAGIC_DELAY		0x444C4159
+#define SOC64_HANDOFF_MAGIC_CLOCK		0x434C4B53
+#define SOC64_HANDOFF_MAGIC_MISC		0x4D495343
+
+#define SOC64_HANDOFF_OFFSET_LENGTH		0x4
+#define SOC64_HANDOFF_OFFSET_DATA		0x10
+#define SOC64_HANDOFF_SIZE			4096
+
+#define SOC64_HANDOFF_BASE			0xFFE3F000
+#define SOC64_HANDOFF_MISC			(SOC64_HANDOFF_BASE + 0x610)
+#define SOC64_HANDOFF_MUX			(SOC64_HANDOFF_BASE + 0x10)
+#define SOC64_HANDOFF_IOCTL			(SOC64_HANDOFF_BASE + 0x1A0)
+#define SOC64_HANDOFF_FPGA			(SOC64_HANDOFF_BASE + 0x330)
+#define SOC64_HANDOFF_DELAY			(SOC64_HANDOFF_BASE + 0x3F0)
+#define SOC64_HANDOFF_CLOCK			(SOC64_HANDOFF_BASE + 0x580)
 
 #ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x608)
-#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x60C)
+#define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x60C)
 #else
-#define SOC64_HANDOFF_CLOCK_OSC	(SOC64_HANDOFF_BASE + 0x5fc)
-#define SOC64_HANDOFF_CLOCK_FPGA	(SOC64_HANDOFF_BASE + 0x600)
+#define SOC64_HANDOFF_CLOCK_OSC			(SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA		(SOC64_HANDOFF_BASE + 0x600)
 #endif
 
-#define SOC64_HANDOFF_SIZE		4096
-
 #endif /* _HANDOFF_SOC64_H_ */