diff mbox series

[v1,03/22] arm: socfpga: dm: Add firewall support for Agilex and Diamond Mesa

Message ID 20200922094930.100855-4-elly.siew.chin.lim@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Add Intel Diamond Mesa SoC support | expand

Commit Message

Siew Chin Lim Sept. 22, 2020, 9:49 a.m. UTC
Disable the MPFE firewall for SMMU and HMC adapter for
Agilex and Diamond Mesa.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/firewall.c                   | 10 ++++++++++
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |  1 +
 arch/arm/mach-socfpga/include/mach/firewall.h      |  6 ++++++
 3 files changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c
index 69229dc651..b87cc8aa69 100644
--- a/arch/arm/mach-socfpga/firewall.c
+++ b/arch/arm/mach-socfpga/firewall.c
@@ -104,4 +104,14 @@  void firewall_setup(void)
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA);
 	writel(SYSMGR_DMAPERIPH_ALL_NS,
 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_DMA_PERIPH);
+
+#if defined(CONFIG_TARGET_SOCFPGA_AGILEX) || defined(CONFIG_TARGET_SOCFPGA_DM)
+	/* Disable the MPFE Firewall for SMMU */
+	writel(FIREWALL_MPFE_SCR_DISABLE_ALL, SOCFPGA_FW_MPFE_SCR_ADDRESS +
+					      FW_MPFE_SCR_HMC);
+	/* Disable MPFE Firewall for HMC adapter (ECC) */
+	writel(FIREWALL_MPFE_SCR_DISABLE_MPU, SOCFPGA_FW_MPFE_SCR_ADDRESS +
+					      FW_MPFE_SCR_HMC_ADAPTOR);
+#endif
+
 }
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index eef88a7fc3..26bd52c907 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -10,6 +10,7 @@ 
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_FW_MPFE_SCR_ADDRESS		0xf8020000
 #if defined(CONFIG_TARGET_SOCFPGA_AGILEX) || defined(CONFIG_TARGET_SOCFPGA_DM)
 #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020200
 #else
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..a2face0570 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -75,6 +75,8 @@  struct socfpga_firwall_l4_sys {
 };
 
 #define FIREWALL_L4_DISABLE_ALL		(BIT(0) | BIT(24) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_ALL	(BIT(0) | BIT(8) | BIT(16))
+#define FIREWALL_MPFE_SCR_DISABLE_MPU	BIT(0)
 #define FIREWALL_BRIDGE_DISABLE_ALL	(~0)
 
 /* Cache coherency unit (CCU) registers */
@@ -120,6 +122,10 @@  struct socfpga_firwall_l4_sys {
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT		0x98
 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT	0x9c
 
+/* Firewall MPFE SCR Registers */
+#define FW_MPFE_SCR_HMC					0x00
+#define FW_MPFE_SCR_HMC_ADAPTOR				0x04
+
 #define MPUREGION0_ENABLE				BIT(0)
 #define NONMPUREGION0_ENABLE				BIT(8)