From patchwork Tue Sep 22 09:49:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1368907 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Bwc7k4V8Zz9sTC for ; Tue, 22 Sep 2020 19:53:22 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2D5578260D; Tue, 22 Sep 2020 11:50:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 297F8825C3; Tue, 22 Sep 2020 11:49:52 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AEB5D825B8 for ; Tue, 22 Sep 2020 11:49:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: 0mI+Mhbz9NfXnnFWgzfOZ4RF1PAECeVFIrhZ5Y6rIgxnfbRyqZ2KkQFjTh/+/O2NbtJMX58x1H amJKrC5dhLqA== X-IronPort-AV: E=McAfee;i="6000,8403,9751"; a="148322192" X-IronPort-AV: E=Sophos;i="5.77,290,1596524400"; d="scan'208";a="148322192" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Sep 2020 02:49:36 -0700 IronPort-SDR: oC4FYwI0En40HGT0ztBhNhA2eoV1a3UMBRqVn9BXPhPLUWHjWI9MfR+XzisEnmNIrsaK/e9qtN ehu53oB3Nfxg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,290,1596524400"; d="scan'208";a="382255792" Received: from sj-nx25.altera.com ([10.142.100.216]) by orsmga001.jf.intel.com with ESMTP; 22 Sep 2020 02:49:36 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Tien Fong Chee , Dalon Westergreen , Siew Chin Lim Subject: [PATCH v1 15/22] arm: socfpga: dm: Add clock manager for Diamond Mesa Date: Tue, 22 Sep 2020 02:49:23 -0700 Message-Id: <20200922094930.100855-16-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20200922094930.100855-1-elly.siew.chin.lim@intel.com> References: <20200922094930.100855-1-elly.siew.chin.lim@intel.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/clock_manager_dm.c | 79 ++++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 + .../mach-socfpga/include/mach/clock_manager_dm.h | 14 ++++ 3 files changed, 95 insertions(+) create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_dm.h diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c b/arch/arm/mach-socfpga/clock_manager_dm.c new file mode 100644 index 0000000000..cdf096cd8b --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_dm.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(socfpga_dm_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(DM_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(DM_L4_SYS_FREE_CLK); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(DM_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(DM_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(DM_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 0f0cb230fa..a164f47bda 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -26,6 +26,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #include #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) #include +#elif defined(CONFIG_TARGET_SOCFPGA_DM) +#include #endif #endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h new file mode 100644 index 0000000000..a355fda692 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Intel Corporation + */ + +#ifndef _CLOCK_MANAGER_DM_ +#define _CLOCK_MANAGER_DM_ + +unsigned long cm_get_mpu_clk_hz(void); + +#include +#include "../../../../../drivers/clk/altera/clk-dm.h" + +#endif /* _CLOCK_MANAGER_DM_ */