From patchwork Wed Sep 16 14:10:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Cerveny X-Patchwork-Id: 1366093 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=computer.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BscFc0HRJz9sSC for ; Thu, 17 Sep 2020 22:48:01 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E6362823C3; Thu, 17 Sep 2020 14:47:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=computer.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1AAC982353; Wed, 16 Sep 2020 16:11:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from dmz.c-home.cz (gw.c-home.cz [89.24.150.100]) by phobos.denx.de (Postfix) with ESMTP id 7DA2582320 for ; Wed, 16 Sep 2020 16:11:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=computer.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=m.cerveny@computer.org Received: from ubuntu1804.c-home.cz (unifi.c-home.cz [192.168.1.239]) by dmz.c-home.cz (8.14.4+Sun/8.14.4) with ESMTP id 08GEB1MQ009756; Wed, 16 Sep 2020 16:11:18 +0200 (CEST) From: Martin Cerveny To: Maxime Ripard Cc: Martin Cerveny , Anatolij Gustschin , Heinrich Schuchardt , Icenowy Zheng , Jagan Teki , Mark Kettenis , Masahiro Yamada , Michael Walle , Simon Glass , u-boot@lists.denx.de Subject: [PATCH 4/5] arm: dts: v3s: Add support for simple-framebuffer with DE2/TCON Date: Wed, 16 Sep 2020 16:10:51 +0200 Message-Id: <20200916141052.4808-5-m.cerveny@computer.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200916141052.4808-1-m.cerveny@computer.org> References: <20200916141052.4808-1-m.cerveny@computer.org> X-Mailman-Approved-At: Thu, 17 Sep 2020 14:47:20 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add support for DE2 and TCON connected LCD display. Add support for export as "allwinner,simple-framebuffer" with "mixer0-lcd0" pipeline. Signed-off-by: Martin Cerveny --- arch/arm/dts/sun8i-v3s.dtsi | 128 ++++++++++++++++++++++++++++++++++-- 1 file changed, 124 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi index ebefc0fefe..59ad5945a1 100644 --- a/arch/arm/dts/sun8i-v3s.dtsi +++ b/arch/arm/dts/sun8i-v3s.dtsi @@ -44,12 +44,28 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <&display_clocks CLK_MIXER0>, + <&ccu CLK_TCON0>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -90,12 +106,90 @@ }; }; + de: display-engine { + compatible = "allwinner,sun8i-v3s-display-engine"; + allwinner,pipelines = <&mixer0>; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; + display_clocks: clock@1000000 { + compatible = "allwinner,sun8i-v3s-de2-clk"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@1100000 { + compatible = "allwinner,sun8i-v3s-de2-mixer"; + reg = <0x01100000 0x100000>; + clocks = <&display_clocks 0>, + <&display_clocks 6>; + clock-names = "bus", + "mod"; + resets = <&display_clocks 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon0: endpoint { + remote-endpoint = <&tcon0_in_mixer0>; + }; + }; + }; + }; + + tcon0: lcd-controller@1c0c000 { + compatible = "allwinner,sun8i-v3s-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON0>, + <&ccu CLK_TCON0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + #clock-cells = <0>; + resets = <&ccu RST_BUS_TCON0>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + reg = <0>; + + tcon0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + tcon0_out_lcd: endpoint@0 { + reg = <0>; + }; + }; + }; + }; + mmc0: mmc@01c0f000 { compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; @@ -208,10 +302,12 @@ interrupt-controller; #interrupt-cells = <3>; - uart0_pins_a: uart0@0 { - pins = "PB8", "PB9"; - function = "uart0"; - bias-pull-up; + lcd_pins: lcd-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", + "PE12", "PE13", "PE14", "PE15", "PE16", "PE17", + "PE18", "PE19", "PE23", "PE24"; + function = "lcd"; }; mmc0_pins_a: mmc0@0 { @@ -221,6 +317,22 @@ drive-strength = <30>; bias-pull-up; }; + + pwm0_pins: pwm0-pins { + pins = "PB4"; + function = "pwm0"; + }; + + pwm1_pins: pwm1-pins { + pins = "PB5"; + function = "pwm1"; + }; + + uart0_pins_a: uart0@0 { + pins = "PB8", "PB9"; + function = "uart0"; + bias-pull-up; + }; }; timer@01c20c00 { @@ -280,5 +392,13 @@ #interrupt-cells = <3>; interrupts = ; }; + + pwm: pwm@1c21400 { + compatible = "allwinner,sun7i-a20-pwm"; + reg = <0x01c21400 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; }; };