From patchwork Wed Sep 16 14:10:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Cerveny X-Patchwork-Id: 1366095 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=computer.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BscG265V7z9sSW for ; Thu, 17 Sep 2020 22:48:26 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3CCDB823BC; Thu, 17 Sep 2020 14:47:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=computer.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9CE228234F; Wed, 16 Sep 2020 16:11:28 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from dmz.c-home.cz (gw.c-home.cz [89.24.150.100]) by phobos.denx.de (Postfix) with ESMTP id 4C43882329 for ; Wed, 16 Sep 2020 16:11:24 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=computer.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=m.cerveny@computer.org Received: from ubuntu1804.c-home.cz (unifi.c-home.cz [192.168.1.239]) by dmz.c-home.cz (8.14.4+Sun/8.14.4) with ESMTP id 08GEB1MP009756; Wed, 16 Sep 2020 16:11:16 +0200 (CEST) From: Martin Cerveny To: Maxime Ripard Cc: Martin Cerveny , Anatolij Gustschin , Heinrich Schuchardt , Icenowy Zheng , Jagan Teki , Mark Kettenis , Masahiro Yamada , Michael Walle , Simon Glass , u-boot@lists.denx.de Subject: [PATCH 3/5] sunxi: video: v3s: Enable LCD support Date: Wed, 16 Sep 2020 16:10:50 +0200 Message-Id: <20200916141052.4808-4-m.cerveny@computer.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200916141052.4808-1-m.cerveny@computer.org> References: <20200916141052.4808-1-m.cerveny@computer.org> X-Mailman-Approved-At: Thu, 17 Sep 2020 14:47:20 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Enable support for V3s LCD display. V3s has 2x VI and 1x UI channels (use UI channel). V3s uses PLL3 (PLL_VIDEO) for both DE2 and TCON0 pixelclock. V3s supports resolution upto 1024x1024. V3s does not support HDMI. Signed-off-by: Martin Cerveny --- arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 ++-- arch/arm/include/asm/arch-sunxi/gpio.h | 1 + arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/sunxi_de2.c | 25 ++++++++++++++++--- drivers/video/sunxi/sunxi_dw_hdmi.c | 2 ++ drivers/video/sunxi/sunxi_lcd.c | 9 ++++++- 6 files changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index ee387127f3..737c3a77fc 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -329,7 +329,7 @@ struct sunxi_ccm_reg { #define AHB_GATE_OFFSET_DE 12 #define AHB_GATE_OFFSET_HDMI 11 #define AHB_GATE_OFFSET_TVE 9 -#ifndef CONFIG_SUNXI_DE2 +#if !defined CONFIG_SUNXI_DE2 || defined CONFIG_MACH_SUN8I_V3S #define AHB_GATE_OFFSET_LCD1 5 #define AHB_GATE_OFFSET_LCD0 4 #else @@ -476,7 +476,7 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_HDMI 11 #define AHB_RESET_OFFSET_HDMI2 10 #define AHB_RESET_OFFSET_TVE 9 -#ifndef CONFIG_SUNXI_DE2 +#if !defined CONFIG_SUNXI_DE2 || defined CONFIG_MACH_SUN8I_V3S #define AHB_RESET_OFFSET_LCD1 5 #define AHB_RESET_OFFSET_LCD0 4 #else @@ -510,6 +510,7 @@ struct sunxi_ccm_reg { #define CCM_DE2_CTRL_PLL_MASK (3 << 24) #define CCM_DE2_CTRL_PLL6_2X (0 << 24) #define CCM_DE2_CTRL_PLL10 (1 << 24) +#define CCM_DE2_CTRL_PLL3_V3S (0 << 24) #define CCM_DE2_CTRL_GATE (0x1 << 31) /* CCU security switch, H3 only */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index d83dfdf605..9b580fbe26 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -181,6 +181,7 @@ enum sunxi_gpio_number { #define SUN5I_GPE_SDC2 3 #define SUN8I_GPE_TWI2 3 #define SUN50I_GPE_TWI2 3 +#define SUN8I_V3S_GPE_LCD0 3 #define SUNXI_GPF_SDC0 2 #define SUNXI_GPF_UART0 4 diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index be0822bfb7..dc0ee2cdef 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -258,6 +258,7 @@ config MACH_SUN8I_V3S select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select ARCH_SUPPORT_PSCI + select SUNXI_DE2 select SUNXI_GEN_SUN6I select SUNXI_DRAM_DW select SUNXI_DRAM_DW_16BIT diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index b657e163f0..49d41eb243 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -26,12 +26,21 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_MACH_SUN8I_V3S +enum { + /* Maximum LCD size we support */ + LCD_MAX_WIDTH = 1024, + LCD_MAX_HEIGHT = 1024, + LCD_MAX_LOG2_BPP = VIDEO_BPP32, +}; +#else enum { /* Maximum LCD size we support */ LCD_MAX_WIDTH = 3840, LCD_MAX_HEIGHT = 2160, LCD_MAX_LOG2_BPP = VIDEO_BPP32, }; +#endif static void sunxi_de2_composer_init(void) { @@ -47,11 +56,19 @@ static void sunxi_de2_composer_init(void) writel(reg_value, SUNXI_SRAMC_BASE + 0x04); #endif +#ifdef CONFIG_MACH_SUN8I_V3S + clock_set_pll3(50000000); + /* pll3 is also used for pixelclock and speed will be recomputed */ + /* Set DE parent to pll3 */ + clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, + CCM_DE2_CTRL_PLL3_V3S); +#else clock_set_pll10(432000000); /* Set DE parent to pll10 */ clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, CCM_DE2_CTRL_PLL10); +#endif /* Set ahb gating to pass */ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); @@ -77,7 +94,8 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, struct de_ui * const de_ui_regs = (struct de_ui *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS + - SUNXI_DE2_MUX_CHAN_SZ * 1); + SUNXI_DE2_MUX_CHAN_SZ * + (IS_ENABLED(CONFIG_MACH_SUN8I_V3S) ? 2 : 1)); struct de_csc * const de_csc_regs = (struct de_csc *)(de_mux_base + SUNXI_DE2_MUX_DCSC_REGS); @@ -104,14 +122,15 @@ static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, for (channel = 0; channel < 4; channel++) { void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS + SUNXI_DE2_MUX_CHAN_SZ * channel); - memset(ch, 0, (channel == 0) ? + memset(ch, 0, (channel == 0 || + (IS_ENABLED(CONFIG_MACH_SUN8I_V3S) && channel == 1)) ? sizeof(struct de_vi) : sizeof(struct de_ui)); } memset(de_bld_regs, 0, sizeof(struct de_bld)); writel(0x00000101, &de_bld_regs->fcolor_ctl); - writel(1, &de_bld_regs->route); + writel(IS_ENABLED(CONFIG_MACH_SUN8I_V3S) ? 2 : 1, &de_bld_regs->route); writel(0, &de_bld_regs->premultiply); writel(0xff000000, &de_bld_regs->bkcolor); diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 01d4b7a11c..899fbe2f7f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -398,6 +398,8 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = { .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv), }; +#ifndef CONFIG_MACH_SUN8I_V3S U_BOOT_DEVICE(sunxi_dw_hdmi) = { .name = "sunxi_dw_hdmi" }; +#endif diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 49bf083a8d..132e970e7d 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -32,6 +32,13 @@ static void sunxi_lcdc_config_pinmux(void) sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0); sunxi_gpio_set_drv(pin, 3); } +#elif defined CONFIG_MACH_SUN8I_V3S + int pin; + + for (pin = SUNXI_GPE(0); pin <= SUNXI_GPE(19); pin++) + sunxi_gpio_set_cfgpin(pin, SUN8I_V3S_GPE_LCD0); + sunxi_gpio_set_cfgpin(SUNXI_GPE(23), SUN8I_V3S_GPE_LCD0); + sunxi_gpio_set_cfgpin(SUNXI_GPE(24), SUN8I_V3S_GPE_LCD0); #endif } @@ -145,7 +152,7 @@ U_BOOT_DRIVER(sunxi_lcd) = { .priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv), }; -#ifdef CONFIG_MACH_SUN50I +#if defined CONFIG_MACH_SUN50I || defined CONFIG_MACH_SUN8I_V3S U_BOOT_DEVICE(sunxi_lcd) = { .name = "sunxi_lcd" };