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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id r78sm17600839qka.95.2020.09.15.07.17.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2020 07:17:43 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Pragnesh Patel , Anup Patel , Rick Chen , Sean Anderson , Bin Meng Subject: [PATCH v5 8/9] riscv: Update Kendryte device tree for new CLINT driver Date: Tue, 15 Sep 2020 10:17:23 -0400 Message-Id: <20200915141724.503929-9-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200915141724.503929-1-seanga2@gmail.com> References: <20200915141724.503929-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean The interrupt controller property is removed from the clint binding because the clint is not an interrupt-controller. That is, no other devices have an interrupt which is controlled by the clint. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- (no changes since v4) Changes in v4: - Remove clock-frequency property from k210 clint binding because we fall back on timebase-frequency Changes in v2: - New arch/riscv/dts/k210.dtsi | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 2546c7d4e0..84cff51c36 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -17,6 +17,8 @@ compatible = "kendryte,k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; dma0 = &dmac0; gpio0 = &gpio0; gpio1 = &gpio1_0; @@ -126,14 +128,13 @@ read-only; }; - clint0: interrupt-controller@2000000 { + clint0: clint@2000000 { #interrupt-cells = <1>; compatible = "kendryte,k210-clint", "riscv,clint0"; reg = <0x2000000 0xC000>; - interrupt-controller; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>; - clocks = <&sysclk K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CLINT>; }; plic0: interrupt-controller@C000000 {