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[108.51.35.162]) by smtp.gmail.com with ESMTPSA id r78sm17600839qka.95.2020.09.15.07.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2020 07:17:40 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Bin Meng , Pragnesh Patel , Anup Patel , Rick Chen , Sean Anderson , Bin Meng Subject: [PATCH v5 5/9] riscv: Clean up initialization in Andes PLIC Date: Tue, 15 Sep 2020 10:17:20 -0400 Message-Id: <20200915141724.503929-6-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200915141724.503929-1-seanga2@gmail.com> References: <20200915141724.503929-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This merges the PLIC initialization code from two functions into one. Signed-off-by: Sean Anderson Reviewed-by: Bin Meng --- This patch builds but has NOT been tested. (no changes since v1) arch/riscv/lib/andes_plic.c | 58 ++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index c2a8fe4d9e..267d6a191b 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -41,53 +41,45 @@ static int enable_ipi(int hart) return 0; } -static int init_plic(void) +int riscv_init_ipi(void) { - struct udevice *dev; - ofnode node; int ret; + long *base = syscon_get_first_range(RISCV_SYSCON_PLIC); + ofnode node; + struct udevice *dev; u32 reg; + if (IS_ERR(base)) + return PTR_ERR(base); + gd->arch.plic = base; + ret = uclass_find_first_device(UCLASS_CPU, &dev); if (ret) return ret; + else if (!dev) + return -ENODEV; - if (dev) { - ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { - const char *device_type; + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; - device_type = ofnode_read_string(node, "device_type"); - if (!device_type) - continue; + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; - if (strcmp(device_type, "cpu")) - continue; + if (strcmp(device_type, "cpu")) + continue; - /* skip if hart is marked as not available */ - if (!ofnode_is_available(node)) - continue; + /* skip if hart is marked as not available */ + if (!ofnode_is_available(node)) + continue; - /* read hart ID of CPU */ - ret = ofnode_read_u32(node, "reg", ®); - if (ret == 0) - enable_ipi(reg); - } - - return 0; + /* read hart ID of CPU */ + ret = ofnode_read_u32(node, "reg", ®); + if (ret == 0) + enable_ipi(reg); } - return -ENODEV; -} - -int riscv_init_ipi(void) -{ - long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC); - - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.plic = ret; - - return init_plic(); + return 0; } int riscv_send_ipi(int hart)