diff mbox series

[RESEND,v5,9/11] ARM: socfpga: Add initial support for ic-automation Moritz III

Message ID 20200911070241.13067-1-n.becker@ic-automation.de
State New
Delegated to: Simon Goldschmidt
Headers show
Series None | expand

Commit Message

Nico Becker Sept. 11, 2020, 7:02 a.m. UTC
Add initial  support for ic-automation Moritz III, which is
an Cyclone V SOM with ethernet, usb, uart. Booting via
sd-card or flash is supported.

Changes for v5:
        - fixed random ethaddr at failure
        - fixed comments

Changes for v4:
        - re-sort list alphabetically
        - c style comments

Changes for v3:
         - Resend via git send-email

Changes for v2:
        - Coding Style cleanup

Signed-off-by: Nico Becker <n.becker@ic-automation.de>
---
 arch/arm/dts/Makefile                         |   1 +
 ...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi |  45 ++
 .../dts/socfpga_cyclone5_ica_moritz_iii.dts   | 123 ++++
 arch/arm/mach-socfpga/Kconfig                 |   8 +
 board/ic-automation/moritz_iii/MAINTAINERS    |   8 +
 board/ic-automation/moritz_iii/Makefile       |   8 +
 .../moritz_iii/moritz_iii_board.c             | 127 ++++
 .../moritz_iii/qts/iocsr_config.h             | 658 ++++++++++++++++++
 .../moritz_iii/qts/pinmux_config.h            | 218 ++++++
 .../ic-automation/moritz_iii/qts/pll_config.h |  83 +++
 .../moritz_iii/qts/sdram_config.h             | 344 +++++++++
 board/ic-automation/moritz_iii/socfpga.c      |   5 +
 configs/socfpga_moritz_iii_defconfig          |  75 ++
 include/configs/socfpga_ica_moritz_iii.h      |  46 ++
 14 files changed, 1749 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
 create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
 create mode 100644 board/ic-automation/moritz_iii/Makefile
 create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
 create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
 create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
 create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
 create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
 create mode 100644 board/ic-automation/moritz_iii/socfpga.c
 create mode 100644 configs/socfpga_moritz_iii_defconfig
 create mode 100644 include/configs/socfpga_ica_moritz_iii.h

Comments

Marek Vasut Sept. 11, 2020, 7:18 a.m. UTC | #1
On 9/11/20 9:02 AM, Nico Becker wrote:
> Add initial  support for ic-automation Moritz III, which is
> an Cyclone V SOM with ethernet, usb, uart. Booting via
> sd-card or flash is supported.
> 
> Changes for v5:

The changelog shouldn't be part of the commmit message, so it goes below
the "---" line. Git then ignores it.

>         - fixed random ethaddr at failure
>         - fixed comments
> 
> Changes for v4:
>         - re-sort list alphabetically
>         - c style comments
> 
> Changes for v3:
>          - Resend via git send-email
> 
> Changes for v2:
>         - Coding Style cleanup
> 
> Signed-off-by: Nico Becker <n.becker@ic-automation.de>
> ---

Here ...

[...]

> +++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot additions
> + *
> + * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (c) 2018 Simon Goldschmidt

I think the copyright assignment needs updating.

> + */
> +
> +#include "socfpga-common-u-boot.dtsi"
> +
> +/{
> +	aliases {
> +		spi0 = "/soc/spi@ff705000";

spi0 = &qspi; should work too ?

[...]

> diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
> new file mode 100644
> index 0000000000..d81f8ea5bf
> --- /dev/null
> +++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2012 Altera Corporation <www.altera.com>
> + * Copyright (C) 2020 Nico Becker ic-automation GmbH <n.becker@ic-automation.de>
> + */
> +
> +#include "socfpga_cyclone5.dtsi"
> +
> +/ {
> +	model = "ic-automation Moritz III";
> +	compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5", "altr,socfpga";
> +
> +	chosen {
> +		bootargs = "earlyprintk";
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@0 {
> +		name = "memory";
> +		device_type = "memory";
> +		reg = <0x0 0x40000000>; /* 1GB */
> +	};
> +
> +	aliases {
> +		/* this allow the ethaddr uboot environmnet variable contents

environment (typo)

> +		 * to be added to the gmac1 device tree blob.
> +		 */
> +		ethernet0 = &gmac1;
> +	};

[...]

[...]

> +++ b/board/ic-automation/moritz_iii/moritz_iii_board.c

[...]

> +int board_late_init(void)
> +{
> +	u8 mac[MAC_LENGTH];
> +	char serial[SERIALNUMBER_LENGTH + 1];
> +	u8 eeprom_data[OVERALL_LENGTH];
> +	u32 calc_crc32;
> +	u32 *read_crc32;
> +	u8 w_data;
> +	int error;
> +	u8 registers[] = {0x02, 0x03, 0x06, 0x07};
> +
> +	for (int i = 0; i < OVERALL_LENGTH; i++)
> +		eeprom_data[i] = 0x00;

Is that a memset() ?

[...]

> +	/* delete environment var first. Otherwise we are unable to set it's value... */
> +	env_set("ethaddr", "");

ethaddr is not a string, so this will fail. Use NULL instead of "" .
But you might just want to check whether ethaddr is set and skip
overwriting it, that way the user can set their own ethaddr and make it
persistent.

> +	struct udevice *bus;
> +	struct udevice *dev;

Move this to the beginning of the function, just like all the other vars.

[...]

> +	/* check crc32 */
> +	calc_crc32 = crc32(0, eeprom_data, OVERALL_LENGTH - CRC32_LENGTH);
> +	read_crc32 = (u32 *)&eeprom_data[SERIALNUMBER_LENGTH + MAC_LENGTH];

Use get_unaligned on the eeprom data, otherwise this will fail on ARM
hardware with CPSR A-bit clear.

> +	if (*read_crc32 != calc_crc32) {
> +		/* print read data is crc32 not valid */
> +		printf("read data:");
> +		for (int i = 0; i < OVERALL_LENGTH; i++)
> +			printf("%02X", eeprom_data[i]);
> +		printf("\n");
> +		/* print crc32 */
> +		printf("read crc32 %08X calc crc32 %08X\n", *read_crc32, calc_crc32);
> +
> +		strncpy(serial, "00000000", 8);
> +		memset((void *)mac, 0x00, 8);
> +	} else {
> +		/* copy serial */
> +		memcpy((void *)serial, (void *)eeprom_data, SERIALNUMBER_LENGTH);

The typecasts are not needed for memset()/memcpy() .

> +		/* copy MAC address */
> +		memcpy((void *)mac, (void *)&eeprom_data[SERIALNUMBER_LENGTH], MAC_LENGTH);
> +	}
> +
> +	serial[SERIALNUMBER_LENGTH] = 0x00;
> +	printf("Serialnumber = %s\n", serial);


[...]

> +++ b/include/configs/socfpga_ica_moritz_iii.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2014 Marek Vasut <marex@denx.de>
> + * Copyright (C) 2020 Nico Becker ic-automation GmbH <n.becker@ic-automation.de>
> + */
> +
> +#ifndef __CONFIG_SOCFPGA_MORITZ_III_H__
> +#define __CONFIG_SOCFPGA_MORITZ_III_H__
> +
> +#include <asm/arch/base_addr_ac5.h>
> +
> +/* Memory configurations */
> +#define PHYS_SDRAM_1_SIZE					0x40000000	/* 1GiB on SoCDK */
> +
> +/* Booting Linux */
> +#define CONFIG_LOADADDR						0x01000000
> +#define CONFIG_SYS_LOAD_ADDR			CONFIG_LOADADDR
> +
> +/* Boot emv */
> +#define CONFIG_EXTRA_ENV_SETTINGS	\
> +	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"	\
> +	"fpgafile=/lib/firmware/socfpga_sram_bridge.rbf\0"	\
> +	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0"	\
> +	"bootm_size=0xa000000\0"	\
> +	"fdt_addr_r=0x02000000\0"	\
> +	"ramdisk_addr_r=0x02300000\0"	\
> +	"socfpga_legacy_reset_compat=1\0"	\
> +	"fpgaloadandenable="			\
> +	"fpga load 0 ${loadaddr} ${filesize};"			\
> +	"echo firmware $fpgafile written to fpga;"			\
> +	"bridge enable; echo bridges enabled;\0"	\
> +	"fpgaload=ext4load mmc 0:2 ${loadaddr} ${fpgafile}; run checkfpgafw;\0"	\

use plain load (with CONFIG_FS_GENERIC) and use && as the load command
might fail. You don't want to run the script if it fails. Also use && in
the rest of the scripts where applicable.

> +	"checkfpgafw="			\
> +	"if test ${filesize} -le 0; then "			\
> +		"echo cant load fpga firmare $fpgafile;"	\
> +	"else "			\
> +		"run fpgaloadandenable;"					\
> +	"fi;\0"			\
> +	"bootargs=console=ttyS0,115200 rootfstype=ext4 root=/dev/mmcblk0p2 rw rootwait\0"	\
> +	"bootcmd=run fpgaload; run mmcload;\0"			\
> +	"mmcload=ext4load mmc 0:2 ${kernel_addr_r} boot/zImage;ext4load mmc 0:2 ${fdt_addr_r} boot/${fdtfile};bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
> +
> +/* The rest of the configuration is shared */
> +#include <configs/socfpga_common.h>
> +
> +#endif	/* __CONFIG_SOCFPGA_MORITZ_III_H__ */
>
Tan, Ley Foon Sept. 11, 2020, 8:36 a.m. UTC | #2
> -----Original Message-----
> From: Nico Becker <n.becker@ic-automation.de>
> Sent: Friday, September 11, 2020 3:03 PM
> To: u-boot@lists.denx.de; marex@denx.de; Tan, Ley Foon
> <ley.foon.tan@intel.com>; simon.k.r.goldschmidt@gmail.com
> Cc: Nico Becker <n.becker@ic-automation.de>
> Subject: [RESEND PATCH v5 9/11] ARM: socfpga: Add initial support for ic-
> automation Moritz III
> 
> Add initial  support for ic-automation Moritz III, which is an Cyclone V SOM
> with ethernet, usb, uart. Booting via sd-card or flash is supported.
> 
> Changes for v5:
>         - fixed random ethaddr at failure
>         - fixed comments
> 
> Changes for v4:
>         - re-sort list alphabetically
>         - c style comments
> 
> Changes for v3:
>          - Resend via git send-email
> 
> Changes for v2:
>         - Coding Style cleanup
> 
> Signed-off-by: Nico Becker <n.becker@ic-automation.de>
> ---
>  arch/arm/dts/Makefile                         |   1 +
>  ...ocfpga_cyclone5_ica_moritz_iii-u-boot.dtsi |  45 ++
>  .../dts/socfpga_cyclone5_ica_moritz_iii.dts   | 123 ++++
>  arch/arm/mach-socfpga/Kconfig                 |   8 +
>  board/ic-automation/moritz_iii/MAINTAINERS    |   8 +
>  board/ic-automation/moritz_iii/Makefile       |   8 +
>  .../moritz_iii/moritz_iii_board.c             | 127 ++++
>  .../moritz_iii/qts/iocsr_config.h             | 658 ++++++++++++++++++
>  .../moritz_iii/qts/pinmux_config.h            | 218 ++++++
>  .../ic-automation/moritz_iii/qts/pll_config.h |  83 +++
>  .../moritz_iii/qts/sdram_config.h             | 344 +++++++++
>  board/ic-automation/moritz_iii/socfpga.c      |   5 +
>  configs/socfpga_moritz_iii_defconfig          |  75 ++
>  include/configs/socfpga_ica_moritz_iii.h      |  46 ++
>  14 files changed, 1749 insertions(+)
>  create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-
> boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
>  create mode 100644 board/ic-automation/moritz_iii/MAINTAINERS
>  create mode 100644 board/ic-automation/moritz_iii/Makefile
>  create mode 100644 board/ic-automation/moritz_iii/moritz_iii_board.c
>  create mode 100644 board/ic-automation/moritz_iii/qts/iocsr_config.h
>  create mode 100644 board/ic-automation/moritz_iii/qts/pinmux_config.h
>  create mode 100644 board/ic-automation/moritz_iii/qts/pll_config.h
>  create mode 100644 board/ic-automation/moritz_iii/qts/sdram_config.h
>  create mode 100644 board/ic-automation/moritz_iii/socfpga.c
>  create mode 100644 configs/socfpga_moritz_iii_defconfig
>  create mode 100644 include/configs/socfpga_ica_moritz_iii.h
> 

What is different from patch https://patchwork.ozlabs.org/project/uboot/patch/20200909120223.10174-1-n.becker@ic-automation.de/ ?
This is patch 9/11?

Regards
Ley Foon
Tan, Ley Foon Oct. 1, 2020, 8:45 a.m. UTC | #3
> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Friday, September 11, 2020 3:19 PM
> To: Nico Becker <n.becker@ic-automation.de>; u-boot@lists.denx.de; Tan,
> Ley Foon <ley.foon.tan@intel.com>; simon.k.r.goldschmidt@gmail.com
> Subject: Re: [RESEND PATCH v5 9/11] ARM: socfpga: Add initial support for
> ic-automation Moritz III
> 
> On 9/11/20 9:02 AM, Nico Becker wrote:
> > Add initial  support for ic-automation Moritz III, which is an Cyclone
> > V SOM with ethernet, usb, uart. Booting via sd-card or flash is
> > supported.
> >
> > Changes for v5:
> 
> The changelog shouldn't be part of the commmit message, so it goes below
> the "---" line. Git then ignores it.
> 
> >         - fixed random ethaddr at failure
> >         - fixed comments
> >
> > Changes for v4:
> >         - re-sort list alphabetically
> >         - c style comments
> >
> > Changes for v3:
> >          - Resend via git send-email
> >
> > Changes for v2:
> >         - Coding Style cleanup
> >
> > Signed-off-by: Nico Becker <n.becker@ic-automation.de>
> > ---
> 
> Here ...
> 
> [...]
> 

Hi Nico

Can you rework as commented by Marek and send new revision of patch?

Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9900b44274..6fbedfe3b3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -352,6 +352,7 @@  dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_de0_nano_soc.dtb		\
 	socfpga_cyclone5_de1_soc.dtb			\
 	socfpga_cyclone5_de10_nano.dtb			\
+	socfpga_cyclone5_ica_moritz_iii.dtb		\
 	socfpga_cyclone5_sockit.dtb			\
 	socfpga_cyclone5_socrates.dtb			\
 	socfpga_cyclone5_sr1500.dtb			\
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
new file mode 100644
index 0000000000..3ba01d1fd9
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
@@ -0,0 +1,45 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (c) 2018 Simon Goldschmidt
+ */
+
+#include "socfpga-common-u-boot.dtsi"
+
+/{
+	aliases {
+		spi0 = "/soc/spi@ff705000";
+		udc0 = &usb1;
+	};
+};
+
+&watchdog0 {
+	status = "disabled";
+};
+
+&mmc {
+	u-boot,dm-pre-reloc;
+};
+
+&qspi {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	clock-frequency = <100000000>;
+	u-boot,dm-pre-reloc;
+};
+
+&porta {
+	bank-name = "porta";
+};
+
+&portb {
+	bank-name = "portb";
+};
+
+&portc {
+	bank-name = "portc";
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
new file mode 100644
index 0000000000..d81f8ea5bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
@@ -0,0 +1,123 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH <n.becker@ic-automation.de>
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "ic-automation Moritz III";
+	compatible = "ic-automation,moritz_iii", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "earlyprintk";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
+  fpga_bridge3: fpga_bridge@ffc25080 {
+		compatible = "altr,socfpga-fpga2sdram-bridge";
+		reg = <0xffc25080 0x4>;
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <1320>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <900>;
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	speed-mode = <0>;
+
+	i2c-switch@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+		i2c@1{
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <1>;
+			mcp_rtc: rtc@6F{
+				compatible = "microchip,mcp7941x";
+				reg = <0x6F>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	speed-mode = <0>;
+
+	gpioexp@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+	};
+
+	e2prom@50 {
+		compatible = "at,24c01";
+		reg = <0x50>;
+	};
+
+	tempsens@48 {
+		compatible = "ti,tmp108";
+		reg = <0x48>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&regulator_3_3v>;
+	vqmmc-supply = <&regulator_3_3v>;
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a3699e82a1..13a9ebac5f 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -118,6 +118,11 @@  config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+	config TARGET_SOCFPGA_ICA_MORITZ_III
+		bool "ic-automation Moritz III (Cyclone V)"
+		select BOARD_LATE_INIT
+		select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_IS1
 	bool "IS1 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -164,6 +169,7 @@  config SYS_BOARD
 	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
 	default "is1" if TARGET_SOCFPGA_IS1
 	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+	default "moritz_iii" if TARGET_SOCFPGA_ICA_MORITZ_III
 	default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -180,6 +186,7 @@  config SYS_VENDOR
 	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+	default "ic-automation" if TARGET_SOCFPGA_ICA_MORITZ_III
 	default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
 	default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
 	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -200,6 +207,7 @@  config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
 	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+	default "socfpga_ica_moritz_iii" if TARGET_SOCFPGA_ICA_MORITZ_III
 	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/board/ic-automation/moritz_iii/MAINTAINERS b/board/ic-automation/moritz_iii/MAINTAINERS
new file mode 100644
index 0000000000..0c8c8ecf21
--- /dev/null
+++ b/board/ic-automation/moritz_iii/MAINTAINERS
@@ -0,0 +1,8 @@ 
+MORITZ III BOARD
+M:	Nico Becker ic-automation GmbH <n.becker@ic-automation.de>
+S:	Maintained
+F:	board/ic-automation/moritz_iii/
+F:	include/configs/socfpga_ica_moritz_iii.h
+F:	configs/socfpga_moritz_iii_defconfig
+F:	arch/arm/dts/socfpga_cyclone5_ica_moritz_iii.dts
+F:	arch/arm/dts/socfpga_cyclone5_ica_moritz_iii-u-boot.dtsi
diff --git a/board/ic-automation/moritz_iii/Makefile b/board/ic-automation/moritz_iii/Makefile
new file mode 100644
index 0000000000..3577c94928
--- /dev/null
+++ b/board/ic-automation/moritz_iii/Makefile
@@ -0,0 +1,8 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+
+obj-y	:= socfpga.o
+obj-y	:= moritz_iii_board.o
\ No newline at end of file
diff --git a/board/ic-automation/moritz_iii/moritz_iii_board.c b/board/ic-automation/moritz_iii/moritz_iii_board.c
new file mode 100644
index 0000000000..e7856fe285
--- /dev/null
+++ b/board/ic-automation/moritz_iii/moritz_iii_board.c
@@ -0,0 +1,127 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 ic-automation GmbH
+ * Nico Becker, ic-automation GmbH <n.becker@ic-automation.de>
+ * Patrick WeiƟ, ic-automation GmbH <p.weiss@ic-automation.de>
+ */
+
+#include <common.h>
+#include <net.h>
+#include <dm/uclass.h>
+#include <i2c.h>
+#include <env_flags.h>
+#include <u-boot/crc.h>
+
+#define I2C_BUS_NUM						1
+#define EEPROM_ADDR						0x50
+#define GPIO_ADDR							0x20
+
+#define SERIALNUMBER_LENGTH		8
+#define MAC_LENGTH						6
+#define CRC32_LENGTH					4
+#define OVERALL_LENGTH				(SERIALNUMBER_LENGTH + MAC_LENGTH + CRC32_LENGTH)
+
+int board_late_init(void)
+{
+	u8 mac[MAC_LENGTH];
+	char serial[SERIALNUMBER_LENGTH + 1];
+	u8 eeprom_data[OVERALL_LENGTH];
+	u32 calc_crc32;
+	u32 *read_crc32;
+	u8 w_data;
+	int error;
+	u8 registers[] = {0x02, 0x03, 0x06, 0x07};
+
+	for (int i = 0; i < OVERALL_LENGTH; i++)
+		eeprom_data[i] = 0x00;
+
+	printf(" _                       _                        _   _\n");
+	printf("(_) ___       __ _ _   _| |_ ___  _ __ ___   __ _| |_(_) ___  _ __\n");
+	printf("| |/ __|____ / _` | | | | __/ _ \\| '_ ` _ \\ / _` | __| |/ _ \\| '_ \\\n");
+	printf("| | (_|_____| (_| | |_| | || (_) | | | | | | (_| | |_| | (_) | | | |\n");
+	printf("|_|\\___|     \\__,_|\\__,_|\\__\\___/|_| |_| |_|\\__,_|\\__|_|\\___/|_| |_|\n");
+	printf("\n");
+
+	/* delete environment var first. Otherwise we are unable to set it's value... */
+	env_set("ethaddr", "");
+
+	struct udevice *bus;
+	struct udevice *dev;
+
+	error = uclass_get_device_by_seq(UCLASS_I2C, I2C_BUS_NUM, &bus);
+	if (error) {
+		printf("cannot get I2C bus 1: uclass_get_device_by_seq failed: %i\n", error);
+		return 0;
+	}
+
+	error = i2c_get_chip(bus, EEPROM_ADDR, 1, &dev);
+	if (error) {
+		printf("Cannot get I2C chip: i2c_get_chip failed: %i\n", error);
+		return 0;
+	}
+
+	/* i2c EEPROM available? */
+	error = dm_i2c_probe(bus, EEPROM_ADDR, 0, &dev);
+	if (error) {
+		printf("Couldn't find i2c eeprom\n");
+		return 0;
+	}
+
+	error = dm_i2c_read(dev, 0, eeprom_data, OVERALL_LENGTH);
+	if (error) {
+		printf("i2c_read failed %d\n", error);
+		return 0;
+	}
+
+	/* check crc32 */
+	calc_crc32 = crc32(0, eeprom_data, OVERALL_LENGTH - CRC32_LENGTH);
+	read_crc32 = (u32 *)&eeprom_data[SERIALNUMBER_LENGTH + MAC_LENGTH];
+	if (*read_crc32 != calc_crc32) {
+		/* print read data is crc32 not valid */
+		printf("read data:");
+		for (int i = 0; i < OVERALL_LENGTH; i++)
+			printf("%02X", eeprom_data[i]);
+		printf("\n");
+		/* print crc32 */
+		printf("read crc32 %08X calc crc32 %08X\n", *read_crc32, calc_crc32);
+
+		strncpy(serial, "00000000", 8);
+		memset((void *)mac, 0x00, 8);
+	} else {
+		/* copy serial */
+		memcpy((void *)serial, (void *)eeprom_data, SERIALNUMBER_LENGTH);
+
+		/* copy MAC address */
+		memcpy((void *)mac, (void *)&eeprom_data[SERIALNUMBER_LENGTH], MAC_LENGTH);
+	}
+
+	serial[SERIALNUMBER_LENGTH] = 0x00;
+	printf("Serialnumber = %s\n", serial);
+
+	if (!is_valid_ethaddr(mac)) {
+		printf("MAC address is invalid, set random MAC\n");
+		net_random_ethaddr(mac);
+	} else {
+		printf("MAC = %02X:%02X:%02X:%02X:%02X:%02X\n",
+			mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+	}
+	error = eth_env_set_enetaddr("ethaddr", mac);
+	if (error)
+		printf("MAC address NOT set. Error: %d\n", error);
+	else
+		printf("MAC address successfully set\n");
+
+	/* set GPIOs */
+	error = i2c_get_chip(bus, GPIO_ADDR, 1, &dev);
+	w_data = 0x00;
+	for (int i = 0 ; i < sizeof(registers) / sizeof(u8); i++) {
+		/* set all values 0 at GPIO-Bank 0 */
+		error = dm_i2c_write(dev, registers[i], &w_data, 1);
+		if (error) {
+			printf("i2c_write GPIO register %X failed. Error: %d\n",
+				registers[i], error);
+			return 0;
+		}
+	}
+	return 0;
+}
diff --git a/board/ic-automation/moritz_iii/qts/iocsr_config.h b/board/ic-automation/moritz_iii/qts/iocsr_config.h
new file mode 100644
index 0000000000..5e82b82457
--- /dev/null
+++ b/board/ic-automation/moritz_iii/qts/iocsr_config.h
@@ -0,0 +1,658 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA IOCSR configuration
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00000000,
+	0x00000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x00060180,
+	0x20000000,
+	0x18000000,
+	0x00018060,
+	0x00000000,
+	0x00004000,
+	0x000300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x00018060,
+	0x06018000,
+	0x06000000,
+	0x00000018,
+	0x00006018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x000C0300,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00080000,
+	0x20000000,
+	0x00000000,
+	0x00000080,
+	0x00020000,
+	0x00004000,
+	0x000300C0,
+	0x10000000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00002000,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x3000B03B,
+	0x00000000,
+	0x0FF00080,
+	0xC0000000,
+	0x0C002C0E,
+	0x80008000,
+	0x1800581D,
+	0x20000000,
+	0x81D80000,
+	0x00018005,
+	0x00020000,
+	0xC0004000,
+	0x28002C0E,
+	0x00B03B00,
+	0x00000030,
+	0xB0008000,
+	0x03000B03,
+	0x60002000,
+	0x14001607,
+	0x08000000,
+	0x60760000,
+	0x00014001,
+	0x00008000,
+	0xB0001000,
+	0x02000B03,
+	0x00000000,
+	0xB03B0008,
+	0xEC00A000,
+	0x00C002C0,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x082000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x204F0000,
+	0x00003001,
+	0x00C00722,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90278000,
+	0x9E001800,
+	0x00600240,
+	0x80090278,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4813C000,
+	0x4F000C00,
+	0x00300120,
+	0xC004813C,
+	0x1204F000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x49034051,
+	0x02081A02,
+	0x802080D0,
+	0x34051406,
+	0x01A02490,
+	0x280D0000,
+	0x5140680A,
+	0x00410340,
+	0xD000001A,
+	0x0680A280,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x78000000,
+	0x01800902,
+	0x002409E0,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x204F0000,
+	0x3C003001,
+	0x00C00481,
+	0x00000FF0,
+	0x4813C000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x6A1C0000,
+	0x9E001800,
+	0x00600240,
+	0x80090278,
+	0x1A870001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4813C000,
+	0x4F000C00,
+	0x00300120,
+	0xC004813C,
+	0x1204F000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0x40680208,
+	0x41034051,
+	0x02081A00,
+	0x80A280D0,
+	0x34051406,
+	0x01A00040,
+	0x080D0002,
+	0x51406802,
+	0x00410340,
+	0xD012481A,
+	0x06802080,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x78000000,
+	0x01800902,
+	0x002409E0,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x204F090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3DD,
+	0xF6D9651E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x01040680,
+	0xD559647A,
+	0x1ECB2CA3,
+	0x48F6D965,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00600391,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8B2CA3DD,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0186,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0x48F6D965,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0xC880090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0x8B2CA3D5,
+	0xF6D9651E,
+	0x034AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0x48F6D965,
+	0x00034AD3,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00008000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0x8B2CA3D9,
+	0xF6D9651E,
+	0x0352D348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1E8B2CA3,
+	0x48F6D145,
+	0x00035292,
+	0x00080200,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000000,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820000,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00000040,
+	0x00010000,
+	0x40002000,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000000,
+	0x00000020,
+	0x00008000,
+	0x20001000,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/ic-automation/moritz_iii/qts/pinmux_config.h b/board/ic-automation/moritz_iii/qts/pinmux_config.h
new file mode 100644
index 0000000000..c96d5c32c3
--- /dev/null
+++ b/board/ic-automation/moritz_iii/qts/pinmux_config.h
@@ -0,0 +1,218 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA PinMux configuration
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	3, /* GENERALIO9 */
+	3, /* GENERALIO10 */
+	3, /* GENERALIO11 */
+	3, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	1, /* GENERALIO15 */
+	1, /* GENERALIO16 */
+	1, /* GENERALIO17 */
+	1, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	1, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	1, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	1, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	1, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	1, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	1, /* GPLMUX40 */
+	1, /* GPLMUX41 */
+	1, /* GPLMUX42 */
+	1, /* GPLMUX43 */
+	1, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	1, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	1, /* GPLMUX53 */
+	1, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	1, /* GPLMUX57 */
+	1, /* GPLMUX58 */
+	1, /* GPLMUX59 */
+	1, /* GPLMUX60 */
+	1, /* GPLMUX61 */
+	1, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/ic-automation/moritz_iii/qts/pll_config.h b/board/ic-automation/moritz_iii/qts/pll_config.h
new file mode 100644
index 0000000000..4bc19765ff
--- /dev/null
+++ b/board/ic-automation/moritz_iii/qts/pll_config.h
@@ -0,0 +1,83 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 200000000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/ic-automation/moritz_iii/qts/sdram_config.h b/board/ic-automation/moritz_iii/qts/sdram_config.h
new file mode 100644
index 0000000000..82263d8678
--- /dev/null
+++ b/board/ic-automation/moritz_iii/qts/sdram_config.h
@@ -0,0 +1,344 @@ 
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			11
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			12
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x3FF
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x10441
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x78
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	12
+#define CALIB_VFIFO_OFFSET	10
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x555504b5
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080471,
+	0x10080570,
+	0x10090006,
+	0x100a0218,
+	0x100b0000,
+	0x10380400,
+	0x10080469,
+	0x100804e8,
+	0x100a0006,
+	0x10090218,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/ic-automation/moritz_iii/socfpga.c b/board/ic-automation/moritz_iii/socfpga.c
new file mode 100644
index 0000000000..48bfe32951
--- /dev/null
+++ b/board/ic-automation/moritz_iii/socfpga.c
@@ -0,0 +1,5 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ */
+#include <common.h>
diff --git a/configs/socfpga_moritz_iii_defconfig b/configs/socfpga_moritz_iii_defconfig
new file mode 100644
index 0000000000..9529c0726b
--- /dev/null
+++ b/configs/socfpga_moritz_iii_defconfig
@@ -0,0 +1,75 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_TARGET_SOCFPGA_ICA_MORITZ_III=y
+CONFIG_SPL_TEXT_BASE=0xFFFF0000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
+CONFIG_DEFAULT_FDT_FILE="socfpga_ica_moritz_iii.dtb"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_DISPLAY_BOARDINFO_LATE is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_MTDIDS_DEFAULT is not set
+# CONFIG_MTDPARTS_DEFAULT is not set
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_ica_moritz_iii"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_DW=y
+CONFIG_MTD=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MII=y
+CONFIG_DM_RESET=y
+CONFIG_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="altera"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+# CONFIG_SPL_WDT is not set
+CONFIG_SYS_PROMPT="M-III > "
+CONFIG_SYS_BOARD="Moritz III"
+CONFIG_SYS_VENDOR="ic-automation GmbH"
diff --git a/include/configs/socfpga_ica_moritz_iii.h b/include/configs/socfpga_ica_moritz_iii.h
new file mode 100644
index 0000000000..9c87a00c97
--- /dev/null
+++ b/include/configs/socfpga_ica_moritz_iii.h
@@ -0,0 +1,46 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ * Copyright (C) 2020 Nico Becker ic-automation GmbH <n.becker@ic-automation.de>
+ */
+
+#ifndef __CONFIG_SOCFPGA_MORITZ_III_H__
+#define __CONFIG_SOCFPGA_MORITZ_III_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE					0x40000000	/* 1GiB on SoCDK */
+
+/* Booting Linux */
+#define CONFIG_LOADADDR						0x01000000
+#define CONFIG_SYS_LOAD_ADDR			CONFIG_LOADADDR
+
+/* Boot emv */
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"	\
+	"fpgafile=/lib/firmware/socfpga_sram_bridge.rbf\0"	\
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR)"\0"	\
+	"bootm_size=0xa000000\0"	\
+	"fdt_addr_r=0x02000000\0"	\
+	"ramdisk_addr_r=0x02300000\0"	\
+	"socfpga_legacy_reset_compat=1\0"	\
+	"fpgaloadandenable="			\
+	"fpga load 0 ${loadaddr} ${filesize};"			\
+	"echo firmware $fpgafile written to fpga;"			\
+	"bridge enable; echo bridges enabled;\0"	\
+	"fpgaload=ext4load mmc 0:2 ${loadaddr} ${fpgafile}; run checkfpgafw;\0"	\
+	"checkfpgafw="			\
+	"if test ${filesize} -le 0; then "			\
+		"echo cant load fpga firmare $fpgafile;"	\
+	"else "			\
+		"run fpgaloadandenable;"					\
+	"fi;\0"			\
+	"bootargs=console=ttyS0,115200 rootfstype=ext4 root=/dev/mmcblk0p2 rw rootwait\0"	\
+	"bootcmd=run fpgaload; run mmcload;\0"			\
+	"mmcload=ext4load mmc 0:2 ${kernel_addr_r} boot/zImage;ext4load mmc 0:2 ${fdt_addr_r} boot/${fdtfile};bootz ${kernel_addr_r} - ${fdt_addr_r}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_MORITZ_III_H__ */