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[88.207.97.133]) by smtp.googlemail.com with ESMTPSA id w8sm7305304ejo.117.2020.09.10.07.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 07:00:14 -0700 (PDT) From: Robert Marko To: u-boot@lists.denx.de Cc: Robert Marko , Luka Perkov Subject: [PATCH v3 2/8] IPQ40xx: clk: Use dt-bindings instead of hardcoding Date: Thu, 10 Sep 2020 16:00:00 +0200 Message-Id: <20200910140006.87531-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200910140006.87531-1-robert.marko@sartura.hr> References: <20200910140006.87531-1-robert.marko@sartura.hr> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Its common to use dt-bindings instead of hard-coding clocks or resets. So lets use the imported Linux GCC bindings on IPQ40xx target. Signed-off-by: Robert Marko Cc: Luka Perkov --- arch/arm/dts/qcom-ipq4019.dtsi | 3 ++- arch/arm/mach-ipq40xx/clock-ipq4019.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 5f78bc5ab9..7b3b5e0248 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -10,6 +10,7 @@ #include "skeleton.dtsi" #include #include +#include / { #address-cells = <1>; @@ -61,7 +62,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; - clock = <&gcc 26>; + clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>; bit-rate = <0xFF>; status = "disabled"; u-boot,dm-pre-reloc; diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c index 7cf98a203c..83a688e625 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -13,6 +13,8 @@ #include #include +#include + struct msm_clk_priv { phys_addr_t base; }; @@ -20,7 +22,7 @@ struct msm_clk_priv { ulong msm_set_rate(struct clk *clk, ulong rate) { switch (clk->id) { - case 26: /*UART1*/ + case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ return 0; break;