From patchwork Wed Sep 9 20:09:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 1361014 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=L1tl3zSO; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BmtSC0tPdz9sTK for ; Thu, 10 Sep 2020 06:10:51 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id CFCAF822E8; Wed, 9 Sep 2020 22:10:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="L1tl3zSO"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 4F631822D1; Wed, 9 Sep 2020 22:09:55 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-qt1-x844.google.com (mail-qt1-x844.google.com [IPv6:2607:f8b0:4864:20::844]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 51D2F822A7 for ; Wed, 9 Sep 2020 22:09:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=seanga2@gmail.com Received: by mail-qt1-x844.google.com with SMTP id g3so3000127qtq.10 for ; Wed, 09 Sep 2020 13:09:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=niyKpHCQkLFnOwx7Hakqk5XsRLJI2KhY2vLGqINCZ5c=; b=L1tl3zSOJaE1O7EcvNCXXfGY77r/wDFwRO9vn888LtaLy6ytIWV5SxrnoZ1GCLoqpn MIuD9o4CUK3CZ9AGE45lV71hAxN9m7XelV398F99MI+XmCDxl4hQsphuW9FmGDD115TL Ardvcj5r5clZZV3PBDAy+B9y3lvLdUuR34Frhez+ojRgXYZeFxgsP73XJ+m+9dTTzYaa hm+ZoDT9jFqhid4/QAK9y51XUUiP1YedZzbNgUP/KYpRIFET1yB5TnCMvBwbb3B6xcFP aivRDffoJQkC3slURXDs3WB7bFFnZ90GO7c4wlIAEjLiA46HEtyR6Jo7AEeErdvrKNxB z0zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=niyKpHCQkLFnOwx7Hakqk5XsRLJI2KhY2vLGqINCZ5c=; b=gp0lQ8aCG/2CgWgujNhxxjokuua8Mva3CiiVjRTTcjZoL2XbmiO+ISiE8VZBZfTyTA gvRL9DABAke7tOKDC5Vqr04KEbEDbZR/373RfArRiEn12wDCVhQ1UZ4vy+Z6tST2mMvV KF6HS3CWfFArM7QFu+JB4VADPIWYAkV7CGKXcp4XcVL0az0FMRgbritHxvoMwQsIgT/F IUJJsYleYILyJENIDs9mDuBBVUevKrhQtxgA26c2dkEnTgWE8ty7FYHKZZ5brES2vWSF gP7OhROqrr0OsuQcUivsJN/Cvs6RjKROvrk6UCIWCK+Sl7uNHMy5LXEXBQkfwXoJNDp1 KAgw== X-Gm-Message-State: AOAM530aTzPGygisZzUrtdm4HVMysy1yPNap/SjsrpqMFvpo7QoMSXcX uk1MEZN7rMAj9gwOD//xyEs4mJxBuIlnqEcI X-Google-Smtp-Source: ABdhPJzGV/ltEZsN44YEPGYy3DoA7kv9/rHM00J+B0GIEvrSmWI3uA/AxUaJIAf22YOfxJMh3ehRqA== X-Received: by 2002:aed:3b7a:: with SMTP id q55mr5025800qte.78.1599682191034; Wed, 09 Sep 2020 13:09:51 -0700 (PDT) Received: from godwin.fios-router.home (pool-108-51-35-162.washdc.fios.verizon.net. [108.51.35.162]) by smtp.gmail.com with ESMTPSA id s30sm4342831qth.65.2020.09.09.13.09.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2020 13:09:50 -0700 (PDT) From: Sean Anderson To: u-boot@lists.denx.de Cc: Anup Patel , Pragnesh Patel , Bin Meng , Rick Chen , Sean Anderson , Pragnesh Patel Subject: [PATCH v4 5/8] riscv: Rework Sifive CLINT as UCLASS_TIMER driver Date: Wed, 9 Sep 2020 16:09:27 -0400 Message-Id: <20200909200930.232174-6-seanga2@gmail.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200909200930.232174-1-seanga2@gmail.com> References: <20200909200930.232174-1-seanga2@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This converts the clint driver from the riscv-specific interface to be a DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously implicitly depended on the CLINT to select REGMAP. Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb), the SiFive CLINT is part of the device tree passed in by qemu. This device tree doesn't have a clocks or clock-frequency property on clint, so we need to fall back on the timebase-frequency property. Perhaps in the future we can get a clock-frequency property added to the qemu dtb. Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller. RISCV_SYSCON_CLINT is retained for this purpose. Signed-off-by: Sean Anderson Reviewed-by: Pragnesh Patel --- This patch builds but has only been tested on the K210 and QEMU. It has NOT been tested on a HiFive. Changes in v4: - Use timer_timebase_fallback Changes in v3: - Don't initialize the IPI in spl_invoke_opensbi. Further testing has revealed it to be unnecessary. arch/riscv/Kconfig | 4 --- arch/riscv/lib/sifive_clint.c | 66 +++++++++++++++++++---------------- drivers/ram/sifive/Kconfig | 2 ++ 3 files changed, 38 insertions(+), 34 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d9155b9bab..aaa3b833a5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -155,10 +155,6 @@ config 64BIT config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index b9a2c649cc..c9704c596f 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -8,9 +8,9 @@ */ #include +#include #include -#include -#include +#include #include #include #include @@ -24,35 +24,19 @@ DECLARE_GLOBAL_DATA_PTR; -int riscv_get_time(u64 *time) -{ - /* ensure timer register base has a sane value */ - riscv_init_ipi(); - - *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); - - return 0; -} - -int riscv_set_timecmp(int hart, u64 cmp) -{ - /* ensure timer register base has a sane value */ - riscv_init_ipi(); - - writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); - - return 0; -} - int riscv_init_ipi(void) { - if (!gd->arch.clint) { - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); + int ret; + struct udevice *dev; - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.clint = ret; - } + ret = uclass_get_device_by_driver(UCLASS_TIMER, + DM_GET_DRIVER(sifive_clint), &dev); + if (ret) + return ret; + + gd->arch.clint = dev_read_addr_ptr(dev); + if (!gd->arch.clint) + return -EINVAL; return 0; } @@ -78,14 +62,36 @@ int riscv_get_ipi(int hart, int *pending) return 0; } +static int sifive_clint_get_count(struct udevice *dev, u64 *count) +{ + *count = readq((void __iomem *)MTIME_REG(dev->priv)); + + return 0; +} + +static const struct timer_ops sifive_clint_ops = { + .get_count = sifive_clint_get_count, +}; + +static int sifive_clint_probe(struct udevice *dev) +{ + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, + { .compatible = "riscv,clint0" }, { } }; U_BOOT_DRIVER(sifive_clint) = { .name = "sifive_clint", - .id = UCLASS_SYSCON, + .id = UCLASS_TIMER, .of_match = sifive_clint_ids, + .probe = sifive_clint_probe, + .ops = &sifive_clint_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig index 6aca22ab2a..31ad0a7e45 100644 --- a/drivers/ram/sifive/Kconfig +++ b/drivers/ram/sifive/Kconfig @@ -9,5 +9,7 @@ config SIFIVE_FU540_DDR bool "SiFive FU540 DDR driver" depends on RAM_SIFIVE default y if TARGET_SIFIVE_FU540 + select REGMAP + select SPL_REGMAP if SPL help This enables DDR support for the platforms based on SiFive FU540 SoC.