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[73.14.175.90]) by smtp.gmail.com with ESMTPSA id w13sm6232663iox.10.2020.09.06.14.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Sep 2020 14:44:45 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Wolfgang Wallner , Bin Meng , Bernhard Messerklinger , Andy Shevchenko , Simon Glass Subject: [PATCH v3 32/57] x86: apl: Allow reading hostbridge base addresses Date: Sun, 6 Sep 2020 15:43:40 -0600 Message-Id: <20200906214405.71632-13-sjg@chromium.org> X-Mailer: git-send-email 2.28.0.526.ge36021eeef-goog In-Reply-To: <20200906214405.71632-1-sjg@chromium.org> References: <20200906214405.71632-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add a few functions to permit reading of various useful base addresses provided by the hostbridge. Signed-off-by: Simon Glass --- (no changes since v1) Changes in v1: - Add comments arch/x86/cpu/apollolake/hostbridge.c | 27 ++++++++++++++++ .../include/asm/arch-apollolake/systemagent.h | 31 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index cb46ec6c0bb..056f7e57a9a 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -40,7 +40,9 @@ enum { PCIEXBAR_PCIEXBAREN = 1 << 0, + BGSM = 0xb4, /* Base GTT Stolen Memory */ TSEG = 0xb8, /* TSEG base */ + TOLUD = 0xbc, }; static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) @@ -165,6 +167,31 @@ static int apl_hostbridge_probe(struct udevice *dev) return 0; } +static ulong sa_read_reg(struct udevice *dev, int reg) +{ + u32 val; + + /* All regions concerned for have 1 MiB alignment */ + dm_pci_read_config32(dev, BGSM, &val); + + return ALIGN_DOWN(val, 1 << 20); +} + +ulong sa_get_tolud_base(struct udevice *dev) +{ + return sa_read_reg(dev, TOLUD); +} + +ulong sa_get_gsm_base(struct udevice *dev) +{ + return sa_read_reg(dev, BGSM); +} + +ulong sa_get_tseg_base(struct udevice *dev) +{ + return sa_read_reg(dev, TSEG); +} + static const struct udevice_id apl_hostbridge_ids[] = { { .compatible = "intel,apl-hostbridge" }, { } diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h index 9e7bd62751a..788a63d7999 100644 --- a/arch/x86/include/asm/arch-apollolake/systemagent.h +++ b/arch/x86/include/asm/arch-apollolake/systemagent.h @@ -35,4 +35,35 @@ */ void enable_bios_reset_cpl(void); +/** + * sa_get_tolud_base() - Get the TOLUD base address + * + * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM + * below 4GB + * + * @dev: hostbridge device + * @return TOLUD address + */ +ulong sa_get_tolud_base(struct udevice *dev); + +/** + * sa_get_gsm_base() - Get the GSM base address + * + * This returns the base of GTT Stolen Memory, marking the start of memory used + * for Graphics Translation Tables. + * + * @dev: hostbridge device + * @return GSM address + */ +ulong sa_get_gsm_base(struct udevice *dev); + +/** + * sa_get_tseg_base() - Get the TSEG base address + * + * This returns the top address of DRAM available below 4GB + * + * @return TSEG base + */ +ulong sa_get_tseg_base(struct udevice *dev); + #endif