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[v3,22/57] x86: apl: Update iomap for ACPI

Message ID 20200906154340.v3.22.I917883a8fac7a88a31608348bfafd057fd49b801@changeid
State Superseded
Delegated to: Bin Meng
Headers show
Series dm: Add programatic generation of ACPI tables (part D) | expand

Commit Message

Simon Glass Sept. 6, 2020, 9:43 p.m. UTC
Add some more definitions to the iomap. These will be used by
ACPI-generation code as well as the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

(no changes since v1)

 arch/x86/include/asm/arch-apollolake/iomap.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
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diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h
index 4ce10170558..21c5f33021a 100644
--- a/arch/x86/include/asm/arch-apollolake/iomap.h
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h
@@ -11,11 +11,27 @@ 
 /* Put p2sb at 0xd0000000 in TPL */
 #define IOMAP_P2SB_BAR		0xd0000000
+#define IOMAP_P2SB_SIZE		0x10000000
 #define IOMAP_SPI_BASE		0xfe010000
 #define IOMAP_ACPI_BASE		0x400
 #define IOMAP_ACPI_SIZE		0x100
+#define PMC_BAR0		0xfe042000
+#define MCH_BASE_ADDRESS	0xfed10000
+#define MCH_SIZE		0x8000
+#ifdef __ACPI__
+#define HPET_BASE_ADDRESS	0xfed00000
+#define SRAM_BASE_0		0xfe900000
+#define SRAM_SIZE_0		(8 * KiB)
+#define SRAM_BASE_2		0xfe902000
+#define SRAM_SIZE_2		(4 * KiB)
  * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial