| Message ID | 20200904125517.1.I23889bc9bd065ae7ac2b17faf2436522848e0568@changeid |
|---|---|
| State | Accepted |
| Commit | 67f9f11f197ff39e4e85e56bca84206ef18ab296 |
| Delegated to: | Patrick Delaunay |
| Headers | show |
| Series | stm32mp: limit size of cacheable DDR in pre-reloc stage | expand |
Hi Patrick On 9/4/20 12:55 PM, Patrick Delaunay wrote: > In pre-reloc stage, U-Boot marks cacheable the DDR limited by > the new config CONFIG_DDR_CACHEABLE_SIZE. > > This patch allows to avoid any speculative access to DDR protected by > firewall and used by OP-TEE; the "no-map" reserved memory > node in DT are assumed after this limit: > STM32_DDR_BASE + DDR_CACHEABLE_SIZE. > > Without security, in basic boot, the value is equal to STM32_DDR_SIZE. > > Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> > --- > > arch/arm/mach-stm32mp/Kconfig | 13 +++++++++++++ > arch/arm/mach-stm32mp/cpu.c | 3 ++- > arch/arm/mach-stm32mp/spl.c | 3 ++- > 3 files changed, 17 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig > index 478fd2f17d..f538d7cb83 100644 > --- a/arch/arm/mach-stm32mp/Kconfig > +++ b/arch/arm/mach-stm32mp/Kconfig > @@ -93,6 +93,19 @@ config SYS_TEXT_BASE > config NR_DRAM_BANKS > default 1 > > +config DDR_CACHEABLE_SIZE > + hex "Size of the DDR marked cacheable in pre-reloc stage" > + default 0x10000000 if TFABOOT > + default 0x40000000 > + help > + Define the size of the DDR marked as cacheable in U-Boot > + pre-reloc stage. > + This option can be useful to avoid speculatif access > + to secured area of DDR used by TF-A or OP-TEE before U-Boot > + initialization. > + The areas marked "no-map" in device tree should be located > + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. > + > config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 > hex "Partition on MMC2 to use to load U-Boot from" > depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION > diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c > index b7fcee2b36..dc170dd6fa 100644 > --- a/arch/arm/mach-stm32mp/cpu.c > +++ b/arch/arm/mach-stm32mp/cpu.c > @@ -230,7 +230,8 @@ static void early_enable_caches(void) > round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), > DCACHE_DEFAULT_OPTION); > else > - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, > + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, > + CONFIG_DDR_CACHEABLE_SIZE, > DCACHE_DEFAULT_OPTION); > } > > diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c > index e84bdad7bf..b679b0a645 100644 > --- a/arch/arm/mach-stm32mp/spl.c > +++ b/arch/arm/mach-stm32mp/spl.c > @@ -138,7 +138,8 @@ void board_init_f(ulong dummy) > * to avoid speculative access and issue in get_ram_size() > */ > if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) > - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, > + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, > + CONFIG_DDR_CACHEABLE_SIZE, > DCACHE_DEFAULT_OPTION); > } > Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Thnaks
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 478fd2f17d..f538d7cb83 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -93,6 +93,19 @@ config SYS_TEXT_BASE config NR_DRAM_BANKS default 1 +config DDR_CACHEABLE_SIZE + hex "Size of the DDR marked cacheable in pre-reloc stage" + default 0x10000000 if TFABOOT + default 0x40000000 + help + Define the size of the DDR marked as cacheable in U-Boot + pre-reloc stage. + This option can be useful to avoid speculatif access + to secured area of DDR used by TF-A or OP-TEE before U-Boot + initialization. + The areas marked "no-map" in device tree should be located + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 hex "Partition on MMC2 to use to load U-Boot from" depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index b7fcee2b36..dc170dd6fa 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -230,7 +230,8 @@ static void early_enable_caches(void) round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), DCACHE_DEFAULT_OPTION); else - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); } diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index e84bdad7bf..b679b0a645 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -138,7 +138,8 @@ void board_init_f(ulong dummy) * to avoid speculative access and issue in get_ram_size() */ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); }
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> --- arch/arm/mach-stm32mp/Kconfig | 13 +++++++++++++ arch/arm/mach-stm32mp/cpu.c | 3 ++- arch/arm/mach-stm32mp/spl.c | 3 ++- 3 files changed, 17 insertions(+), 2 deletions(-)