diff mbox series

[2/3] riscv: Mark riscv_timer_get_count() and sifive_clint_get_count() with 'notrace'

Message ID 20200824144429.12641-3-pragnesh.patel@sifive.com
State New
Delegated to: Andes
Headers show
Series RISC-V tracing support | expand

Commit Message

Pragnesh Patel Aug. 24, 2020, 2:44 p.m. UTC
Mark them as 'notrace' so that it doesn't cause infinite recursion.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
 arch/riscv/lib/sifive_clint.c | 2 +-
 drivers/timer/riscv_timer.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index 3345a17ad2..1cf74a6cf4 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -62,7 +62,7 @@  int riscv_get_ipi(int hart, int *pending)
 	return 0;
 }
 
-static int sifive_clint_get_count(struct udevice *dev, u64 *count)
+static int notrace sifive_clint_get_count(struct udevice *dev, u64 *count)
 {
 	*count = readq((void __iomem *)MTIME_REG(dev->priv));
 
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 449fcfcfd5..342e0354dc 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -16,7 +16,7 @@ 
 #include <timer.h>
 #include <asm/csr.h>
 
-static int riscv_timer_get_count(struct udevice *dev, u64 *count)
+static int notrace riscv_timer_get_count(struct udevice *dev, u64 *count)
 {
 	if (IS_ENABLED(CONFIG_64BIT)) {
 		*count = csr_read(CSR_TIME);