diff mbox series

[v3,04/11] reset: add basic reset controller for pciesys

Message ID 20200820095545.4643-5-linux@fw-web.de
State Accepted
Commit fee276ee315ceff64900777b0b46cdafd88d1cfe
Delegated to: Marek Vasut
Headers show
Series Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622> | expand

Commit Message

Frank Wunderlich Aug. 20, 2020, 9:55 a.m. UTC 
From: Frank Wunderlich <frank-w@public-files.de>

bind reset controller to pciesys

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
---
 drivers/clk/mediatek/clk-mt7622.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

Comments

Frank Wunderlich Aug. 20, 2020, 10:52 a.m. UTC | #1 
> Gesendet: Donnerstag, 20. August 2020 um 11:55 Uhr
> Von: "Frank Wunderlich" <linux@fw-web.de>
> +static int mt7622_pciesys_bind(struct udevice *dev)
> +{
> +	int ret = 0;
> +
> +	if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
> +//	PCIESYS uses in linux also 0x34 = ETHSYS reset controller

sorry, squashed change to wrong commit...will fix it soon

> +	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
> +	if (ret)
> +		debug("Warning: failed to bind reset controller\n");
> +	}
> +
> +	return ret;
> +}
diff mbox series

Patch

diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index bd86b5b974..d53ed69189 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -594,6 +594,20 @@  static int mt7622_pciesys_probe(struct udevice *dev)
 	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs);
 }
 
+static int mt7622_pciesys_bind(struct udevice *dev)
+{
+	int ret = 0;
+
+	if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) {
+//	PCIESYS uses in linux also 0x34 = ETHSYS reset controller
+	ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+	if (ret)
+		debug("Warning: failed to bind reset controller\n");
+	}
+
+	return ret;
+}
+
 static int mt7622_ethsys_probe(struct udevice *dev)
 {
 	return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
@@ -710,6 +724,7 @@  U_BOOT_DRIVER(mtk_clk_pciesys) = {
 	.id = UCLASS_CLK,
 	.of_match = mt7622_pciesys_compat,
 	.probe = mt7622_pciesys_probe,
+	.bind = mt7622_pciesys_bind,
 	.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
 	.ops = &mtk_clk_gate_ops,
 };