From patchwork Mon Aug 17 07:07:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1345686 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=CExWwlnE; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BVQCz4wP8z9sPC for ; Mon, 17 Aug 2020 17:10:07 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A647282282; Mon, 17 Aug 2020 09:08:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1597648108; bh=iwe+I6Y74CHw5pn5FaIPwEkieeXoBxP9lJJcEvCs4gI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=CExWwlnEtXnu9yi6HA2gXU/woCsRvQw7tnjRTvIBD5WUlOrsgdUhXiB5GHXDZ97M8 kHLKjorYBMMcGN4tkALWiiGHRF4XpYTu8EHzi0wSa3Z7DxI8KGKlsK0WwEvWd4tu/m RsbS2S+PD4KbAl+A7vwV9XTvht4Y4nMU2od9XfiGPjL+K862ZCUI9g5l8Ph0NhP1EX ZWRk2erzXQUfZ5ym1ue0gxgED98+zGkyFALCMMUCZJAKnQ1JPvNuND7+RX8gieow0M elMpDJRTNX/H5tWra0fFWNxRaY8J8ghMEZDrz+kB0uP6AYoAsGer8Mvg4kI6uH4L5E hN91ThD0ir9Ug== Received: by phobos.denx.de (Postfix, from userid 109) id 486C482232; Mon, 17 Aug 2020 09:08:16 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B2E58821BE for ; Mon, 17 Aug 2020 09:08:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:105:465:1:1:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id 69B29A1613; Mon, 17 Aug 2020 09:08:09 +0200 (CEST) Received: from smtp1.mailbox.org ([80.241.60.240]) by spamfilter03.heinlein-hosting.de (spamfilter03.heinlein-hosting.de [80.241.56.117]) (amavisd-new, port 10030) with ESMTP id laCsR8GbpxZ0; Mon, 17 Aug 2020 09:08:05 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: sjg@chromium.org, awilliams@marvell.com, trini@konsulko.com, sgarapati@marvell.com, cchavva@marvell.com, Bin Meng Subject: [PATCH v2 08/25] pci: pci-uclass: Add multi entry support for memory regions Date: Mon, 17 Aug 2020 09:07:45 +0200 Message-Id: <20200817070802.1517632-9-sr@denx.de> In-Reply-To: <20200817070802.1517632-1-sr@denx.de> References: <20200817070802.1517632-1-sr@denx.de> MIME-Version: 1.0 X-MBO-SPAM-Probability: X-Rspamd-Score: -0.76 / 15.00 / 15.00 X-Rspamd-Queue-Id: 255961816 X-Rspamd-UID: 20c467 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Suneel Garapati Enable PCI memory regions in ranges property to be of multiple entry. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on PCI bus. Signed-off-by: Suneel Garapati Cc: Simon Glass Cc: Bin Meng Signed-off-by: Stefan Roese Reviewed-by: Simon Glass --- Changes in v2: - Add sandbox test Changes in v1: - Change patch subject - Enhance Kconfig help descrition - Use if() instead of #if arch/sandbox/dts/test.dts | 5 +++-- configs/sandbox_defconfig | 1 + drivers/pci/Kconfig | 10 ++++++++++ drivers/pci/pci-uclass.c | 9 ++++++--- test/dm/pci.c | 22 ++++++++++++++++++++++ 5 files changed, 42 insertions(+), 5 deletions(-) diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 491893a17d..d3c18eee71 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -652,8 +652,9 @@ bus-range = <0x00 0xff>; #address-cells = <3>; #size-cells = <2>; - ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 - 0x01000000 0 0x40000000 0x40000000 0 0x2000>; + ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0 + 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1 + 0x01000000 0 0x40000000 0x40000000 0 0x2000>; sandbox,dev-info = <0x08 0x00 0x1234 0x5678 0x0c 0x00 0x1234 0x5678 0x10 0x00 0x1234 0x5678>; diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index fe11128904..cc2f8c287c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -180,6 +180,7 @@ CONFIG_NVME=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y CONFIG_PCI_SANDBOX=y CONFIG_PHY=y CONFIG_PHY_SANDBOX=y diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 5e0a39396b..1c47a21101 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -43,6 +43,16 @@ config PCI_PNP help Enable PCI memory and I/O space resource allocation and assignment. +config PCI_REGION_MULTI_ENTRY + bool "Enable Multiple entries of region type MEMORY in ranges for PCI" + depends on PCI || DM_PCI + default n + help + Enable PCI memory regions to be of multiple entry. Multiple entry + here refers to allow more than one count of address ranges for MEMORY + region type. This helps to add support for SoC's like OcteonTX/TX2 + where every peripheral is on the PCI bus. + config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" default n diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index cf1bbccbba..19ea3ae9c1 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -936,10 +936,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, } pos = -1; - for (i = 0; i < hose->region_count; i++) { - if (hose->regions[i].flags == type) - pos = i; + if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) { + for (i = 0; i < hose->region_count; i++) { + if (hose->regions[i].flags == type) + pos = i; + } } + if (pos == -1) pos = hose->region_count++; debug(" - type=%d, pos=%d\n", type, pos); diff --git a/test/dm/pci.c b/test/dm/pci.c index fd66ed7899..76490befdf 100644 --- a/test/dm/pci.c +++ b/test/dm/pci.c @@ -354,3 +354,25 @@ static int dm_test_pci_on_bus(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_pci_on_bus, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); + +/* + * Test support for multiple memory regions enabled via + * CONFIG_PCI_REGION_MULTI_ENTRY. When this feature is not enabled, + * only the last region of one type is stored. In this test-case, + * we have 2 memory regions, the first at 0x3000.0000 and the 2nd + * at 0x3100.0000. A correct test results now in BAR1 located at + * 0x3000.0000. + */ +static int dm_test_pci_region_multi(struct unit_test_state *uts) +{ + struct udevice *dev; + ulong mem_addr; + + /* Test memory BAR1 on bus#1 */ + ut_assertok(dm_pci_bus_find_bdf(PCI_BDF(1, 0x08, 0), &dev)); + mem_addr = dm_pci_read_bar32(dev, 1); + ut_asserteq(mem_addr, 0x30000000); + + return 0; +} +DM_TEST(dm_test_pci_region_multi, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);