From patchwork Mon Aug 17 04:34:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 1345610 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BVLqS688hz9sTH for ; Mon, 17 Aug 2020 14:37:08 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4728182258; Mon, 17 Aug 2020 06:35:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 489EE82262; Mon, 17 Aug 2020 06:35:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 567D482259 for ; Mon, 17 Aug 2020 06:35:11 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=chee.hong.ang@intel.com IronPort-SDR: rC8i9RyNJvMZa0A18ScEoyb1mbXdwNFdmrrjXn9Bs18lu2mSY3/QtkZRA2VnczyMTSC85pXl2K XqAFQtYWlX4w== X-IronPort-AV: E=McAfee;i="6000,8403,9715"; a="155729090" X-IronPort-AV: E=Sophos;i="5.76,322,1592895600"; d="scan'208";a="155729090" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Aug 2020 21:35:10 -0700 IronPort-SDR: AdFxAXG+ayECOaiPqiEo5o9f4ochZOmcQWX07iA4nFQKqk0ZCFc5qYZ/MH/Yt3bU3Mw5UCf7kO WCMDRjJ/4QWA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,322,1592895600"; d="scan'208";a="328499952" Received: from ppglcf0010.png.intel.com ([10.226.229.26]) by fmsmga002.fm.intel.com with ESMTP; 16 Aug 2020 21:35:08 -0700 From: Chee Hong Ang To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Tom Rini , Ching Liang See , Ley Foon , Chee Hong Ang , Tien Fong , Siew Chin Subject: [PATCH v1 11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver Date: Mon, 17 Aug 2020 12:34:26 +0800 Message-Id: <20200817043431.28718-12-chee.hong.ang@intel.com> X-Mailer: git-send-email 2.19.0 In-Reply-To: <20200817043431.28718-1-chee.hong.ang@intel.com> References: <20200817043431.28718-1-chee.hong.ang@intel.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service provided by ATF to enable/disable the SOCFPGA bridges. Signed-off-by: Chee Hong Ang --- arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index e5eb7f4aeb..79b8044aa0 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -5,11 +5,14 @@ */ #include +#include #include #include +#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -55,6 +58,12 @@ void socfpga_per_reset_all(void) void socfpga_bridges_reset(int enable) { +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 arg = enable; + + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0)) + hang(); +#else u32 reg; if (enable) { @@ -101,6 +110,7 @@ void socfpga_bridges_reset(int enable) /* Disable NOC timeout */ writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT); } +#endif } /*