diff mbox series

[v1,11/16] arm: socfpga: soc64: Add ATF support for Reset Manager driver

Message ID 20200817043431.28718-12-chee.hong.ang@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Enable ARM Trusted Firmware for U-Boot | expand

Commit Message

Ang, Chee Hong Aug. 17, 2020, 4:34 a.m. UTC
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Tan, Ley Foon Sept. 11, 2020, 2:08 a.m. UTC | #1
> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang@intel.com>
> Sent: Monday, August 17, 2020 12:34 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Tom Rini <trini@konsulko.com>; See,
> Chin Liang <chin.liang.see@intel.com>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; Ang, Chee Hong <chee.hong.ang@intel.com>;
> Chee, Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [PATCH v1 11/16] arm: socfpga: soc64: Add ATF support for Reset
> Manager driver
> 
> In non-secure mode (EL2), Reset Manager driver calls the SMC/PSCI service
> provided by ATF to enable/disable the SOCFPGA bridges.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
>  arch/arm/mach-socfpga/reset_manager_s10.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c
> b/arch/arm/mach-socfpga/reset_manager_s10.c
> index e5eb7f4aeb..79b8044aa0 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> @@ -5,11 +5,14 @@
>   */
> 
>  #include <common.h>
> +#include <hang.h>
>  #include <asm/io.h>
>  #include <asm/arch/reset_manager.h>
> +#include <asm/arch/smc_api.h>
>  #include <asm/arch/system_manager.h>
>  #include <dt-bindings/reset/altr,rst-mgr-s10.h>
>  #include <linux/iopoll.h>
> +#include <linux/intel-smc.h>
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -55,6 +58,12 @@ void socfpga_per_reset_all(void)
> 
>  void socfpga_bridges_reset(int enable)
>  {
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> +	u64 arg = enable;
> +
> +	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL,
> 0))
> +		hang();
Why need to hang if failed to enable bridge? Can add the error message and return.


Regards
Ley Foon
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index e5eb7f4aeb..79b8044aa0 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -5,11 +5,14 @@ 
  */
 
 #include <common.h>
+#include <hang.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/smc_api.h>
 #include <asm/arch/system_manager.h>
 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
 #include <linux/iopoll.h>
+#include <linux/intel-smc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -55,6 +58,12 @@  void socfpga_per_reset_all(void)
 
 void socfpga_bridges_reset(int enable)
 {
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	u64 arg = enable;
+
+	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_BRIDGES, &arg, 1, NULL, 0))
+		hang();
+#else
 	u32 reg;
 
 	if (enable) {
@@ -101,6 +110,7 @@  void socfpga_bridges_reset(int enable)
 		/* Disable NOC timeout */
 		writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
 	}
+#endif
 }
 
 /*