diff mbox series

[v1,10/16] net: designware: socfpga: Add ATF support for MAC driver

Message ID 20200817043431.28718-11-chee.hong.ang@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Enable ARM Trusted Firmware for U-Boot | expand

Commit Message

Ang, Chee Hong Aug. 17, 2020, 4:34 a.m. UTC
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 drivers/net/dwmac_socfpga.c | 43 +++++++++++++++++++++++++++++++++----
 1 file changed, 39 insertions(+), 4 deletions(-)

Comments

Tan, Ley Foon Sept. 25, 2020, 8:14 a.m. UTC | #1
> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang@intel.com>
> Sent: Monday, August 17, 2020 12:34 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Tom Rini <trini@konsulko.com>; See,
> Chin Liang <chin.liang.see@intel.com>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; Ang, Chee Hong <chee.hong.ang@intel.com>;
> Chee, Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [PATCH v1 10/16] net: designware: socfpga: Add ATF support for
> MAC driver
> 
> In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided
> by ATF to setup the PHY interface.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
>  drivers/net/dwmac_socfpga.c | 43
> +++++++++++++++++++++++++++++++++----
>  1 file changed, 39 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
> index e93561dffa..0dd5a54405 100644
> --- a/drivers/net/dwmac_socfpga.c
> +++ b/drivers/net/dwmac_socfpga.c
> @@ -17,7 +17,9 @@
>  #include <dm/device_compat.h>
>  #include <linux/err.h>
> 
> +#include <asm/arch/smc_api.h>
>  #include <asm/arch/system_manager.h>
> +#include <linux/intel-smc.h>
> 
>  struct dwmac_socfpga_platdata {
>  	struct dw_eth_pdata	dw_eth_pdata;
> @@ -64,6 +66,35 @@ static int dwmac_socfpga_ofdata_to_platdata(struct
> udevice *dev)
>  	return designware_eth_ofdata_to_platdata(dev);
>  }
> 
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) static int
> +dwmac_socfpga_fw_setphy(struct udevice *dev, u32 modereg) {
> +	struct ofnode_phandle_args pargs;
> +	u64 args[2];
> +	int ret;
> +
> +	ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
> +					 1, 0, &pargs);
> +	if (ret) {
> +		dev_err(dev, "Failed to get syscon: %d\n", ret);
> +		return ret;
> +	}
> +
> +	if (pargs.args_count < 1) {
> +		dev_err(dev, "No syscon args found\n");
> +		return -EINVAL;
> +	}
> +
Why need get from "altr,sysmgr-syscon" phandle again?
dwmac_socfpga_ofdata_to_platdata() already doing same thing.

> +	args[0] = ((u64)pargs.args[0] - SYSMGR_SOC64_EMAC0) >> 2;
> +	args[1] = modereg;
> +
> +	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
> +		return -EIO;
> +
> +	return 0;
> +}
> +#endif
> +
>  static int dwmac_socfpga_probe(struct udevice *dev)  {
>  	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
> @@ -71,7 +102,6 @@ static int dwmac_socfpga_probe(struct udevice *dev)
>  	struct reset_ctl_bulk reset_bulk;
>  	int ret;
>  	u32 modereg;
> -	u32 modemask;
> 
>  	switch (edata->phy_interface) {
>  	case PHY_INTERFACE_MODE_MII:
> @@ -97,9 +127,14 @@ static int dwmac_socfpga_probe(struct udevice *dev)
> 
>  	reset_assert_bulk(&reset_bulk);
> 
> -	modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata-
> >reg_shift;
> -	clrsetbits_le32(pdata->phy_intf, modemask,
> -			modereg << pdata->reg_shift);
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> +	ret = dwmac_socfpga_fw_setphy(dev, modereg);
> +	if (ret)
> +		return ret;
> +#else
> +	clrsetbits_le32(pdata->phy_intf,
> SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
> +			pdata->reg_shift, modereg << pdata->reg_shift);
> #endif
Move the #ifdef .. #endif switch to dwmac_socfpga_fw_setphy(). 
So, that it can call to dwmac_socfpga_fw_setphy() directly here with #ifdef.
For "[PATCH v1 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver" patch, also change the same.


Regards
Ley Foon
diff mbox series

Patch

diff --git a/drivers/net/dwmac_socfpga.c b/drivers/net/dwmac_socfpga.c
index e93561dffa..0dd5a54405 100644
--- a/drivers/net/dwmac_socfpga.c
+++ b/drivers/net/dwmac_socfpga.c
@@ -17,7 +17,9 @@ 
 #include <dm/device_compat.h>
 #include <linux/err.h>
 
+#include <asm/arch/smc_api.h>
 #include <asm/arch/system_manager.h>
+#include <linux/intel-smc.h>
 
 struct dwmac_socfpga_platdata {
 	struct dw_eth_pdata	dw_eth_pdata;
@@ -64,6 +66,35 @@  static int dwmac_socfpga_ofdata_to_platdata(struct udevice *dev)
 	return designware_eth_ofdata_to_platdata(dev);
 }
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static int dwmac_socfpga_fw_setphy(struct udevice *dev, u32 modereg)
+{
+	struct ofnode_phandle_args pargs;
+	u64 args[2];
+	int ret;
+
+	ret = dev_read_phandle_with_args(dev, "altr,sysmgr-syscon", NULL,
+					 1, 0, &pargs);
+	if (ret) {
+		dev_err(dev, "Failed to get syscon: %d\n", ret);
+		return ret;
+	}
+
+	if (pargs.args_count < 1) {
+		dev_err(dev, "No syscon args found\n");
+		return -EINVAL;
+	}
+
+	args[0] = ((u64)pargs.args[0] - SYSMGR_SOC64_EMAC0) >> 2;
+	args[1] = modereg;
+
+	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_PHYINTF, args, 2, NULL, 0))
+		return -EIO;
+
+	return 0;
+}
+#endif
+
 static int dwmac_socfpga_probe(struct udevice *dev)
 {
 	struct dwmac_socfpga_platdata *pdata = dev_get_platdata(dev);
@@ -71,7 +102,6 @@  static int dwmac_socfpga_probe(struct udevice *dev)
 	struct reset_ctl_bulk reset_bulk;
 	int ret;
 	u32 modereg;
-	u32 modemask;
 
 	switch (edata->phy_interface) {
 	case PHY_INTERFACE_MODE_MII:
@@ -97,9 +127,14 @@  static int dwmac_socfpga_probe(struct udevice *dev)
 
 	reset_assert_bulk(&reset_bulk);
 
-	modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift;
-	clrsetbits_le32(pdata->phy_intf, modemask,
-			modereg << pdata->reg_shift);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	ret = dwmac_socfpga_fw_setphy(dev, modereg);
+	if (ret)
+		return ret;
+#else
+	clrsetbits_le32(pdata->phy_intf, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK <<
+			pdata->reg_shift, modereg << pdata->reg_shift);
+#endif
 
 	reset_release_bulk(&reset_bulk);