diff mbox series

[v1,09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver

Message ID 20200817043431.28718-10-chee.hong.ang@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series Enable ARM Trusted Firmware for U-Boot | expand

Commit Message

Ang, Chee Hong Aug. 17, 2020, 4:34 a.m. UTC
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 drivers/mmc/socfpga_dw_mmc.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Tan, Ley Foon Sept. 25, 2020, 7:41 a.m. UTC | #1
> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang@intel.com>
> Sent: Monday, August 17, 2020 12:34 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Tom Rini <trini@konsulko.com>; See,
> Chin Liang <chin.liang.see@intel.com>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; Ang, Chee Hong <chee.hong.ang@intel.com>;
> Chee, Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [PATCH v1 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC
> driver
> 
> In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided
> by ATF to set SDMMC's DRVSEL and SMPLSEL.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
>  drivers/mmc/socfpga_dw_mmc.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/mmc/socfpga_dw_mmc.c
> b/drivers/mmc/socfpga_dw_mmc.c index 0022f943bd..a58ea472b9 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -6,6 +6,7 @@
>  #include <common.h>
>  #include <log.h>
>  #include <asm/arch/clock_manager.h>
> +#include <asm/arch/smc_api.h>
>  #include <asm/arch/system_manager.h>
>  #include <clk.h>
>  #include <dm.h>
> @@ -13,6 +14,7 @@
>  #include <errno.h>
>  #include <fdtdec.h>
>  #include <dm/device_compat.h>
> +#include <linux/intel-smc.h>
>  #include <linux/libfdt.h>
>  #include <linux/err.h>
>  #include <malloc.h>
> @@ -46,6 +48,20 @@ static void socfpga_dwmci_reset(struct udevice *dev)
>  	reset_deassert_bulk(&reset_bulk);
>  }
> 
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) static void
> +socfpga_dwmci_fw_clksel(u32 sdmmc_mask) {
> +	u64 args[2];
> +
> +	/* drvsel */
> +	args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
> +	/* smplsel */
> +	args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
> +	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2,
> NULL, 0))
> +		dev_err(host->dev, "SMC call failed in %s\n", __func__); }
> #endif
> +
>  static void socfpga_dwmci_clksel(struct dwmci_host *host)  {
>  	struct dwmci_socfpga_priv_data *priv = host->priv; @@ -58,10
> +74,14 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> 
>  	debug("%s: drvsel %d smplsel %d\n", __func__,
>  	      priv->drvsel, priv->smplsel);
> +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
> +	socfpga_dwmci_fw_clksel(sdmmc_mask);
> +#else
>  	writel(sdmmc_mask, socfpga_get_sysmgr_addr() +
> SYSMGR_SDMMC);
> 
>  	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
>  		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
> +#endif
> 
>  	/* Enable SDMMC clock */
>  	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,
> --
> 2.19.0

Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff mbox series

Patch

diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 0022f943bd..a58ea472b9 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -6,6 +6,7 @@ 
 #include <common.h>
 #include <log.h>
 #include <asm/arch/clock_manager.h>
+#include <asm/arch/smc_api.h>
 #include <asm/arch/system_manager.h>
 #include <clk.h>
 #include <dm.h>
@@ -13,6 +14,7 @@ 
 #include <errno.h>
 #include <fdtdec.h>
 #include <dm/device_compat.h>
+#include <linux/intel-smc.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
 #include <malloc.h>
@@ -46,6 +48,20 @@  static void socfpga_dwmci_reset(struct udevice *dev)
 	reset_deassert_bulk(&reset_bulk);
 }
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+static void socfpga_dwmci_fw_clksel(u32 sdmmc_mask)
+{
+	u64 args[2];
+
+	/* drvsel */
+	args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7;
+	/* smplsel */
+	args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7;
+	if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0))
+		dev_err(host->dev, "SMC call failed in %s\n", __func__);
+}
+#endif
+
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
 	struct dwmci_socfpga_priv_data *priv = host->priv;
@@ -58,10 +74,14 @@  static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+	socfpga_dwmci_fw_clksel(sdmmc_mask);
+#else
 	writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
 		readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
+#endif
 
 	/* Enable SDMMC clock */
 	setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN,