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Mon, 10 Aug 2020 14:59:14 +0000 (UTC) From: Frank Wunderlich To: u-boot@lists.denx.de Cc: Frank Wunderlich , GSS_MTK_Uboot_upstream , Ryder Lee , Weijie Gao , Lukasz Majewski Subject: [PATCH 5/5] dts: r64: add sata- and asm_sel nodes Date: Mon, 10 Aug 2020 16:58:51 +0200 Message-Id: <20200810145851.43381-6-linux@fw-web.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200810145851.43381-1-linux@fw-web.de> References: <20200810145851.43381-1-linux@fw-web.de> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 10 Aug 2020 17:00:31 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Frank Wunderlich asm_sel is for switching between sata and pcie mode on r64 there is GPIO90 connected to ASM1480 which switches RX/TX pairs to PCIe/SATA connector output-low means sata-controller is active with 2020-10 now reg is also needed for the phy itself Signed-off-by: Frank Wunderlich --- arch/arm/dts/mt7622-bpi-r64.dts | 9 +++++++ arch/arm/dts/mt7622.dtsi | 44 +++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/arm/dts/mt7622-bpi-r64.dts b/arch/arm/dts/mt7622-bpi-r64.dts index c89e816878..51287cea3a 100644 --- a/arch/arm/dts/mt7622-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bpi-r64.dts @@ -235,3 +235,12 @@ full-duplex; }; }; + +&gpio { + /*gpio 90 for setting mode to sata*/ + asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index fec071643e..2802909671 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "mediatek,mt7622"; @@ -270,6 +271,49 @@ }; }; + sata: sata@1a200000 { + compatible = "mediatek,mtk-ahci"; +// reg = <0 0x1a200000 0 0x1100>; + reg = <0x1a200000 0x1100>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + ports-implemented = <0x1>; +/* + interrupts = ; + interrupt-names = "hostc"; + clocks = <&pciesys CLK_SATA_AHB_EN>, + <&pciesys CLK_SATA_AXI_EN>, + <&pciesys CLK_SATA_ASIC_EN>, + <&pciesys CLK_SATA_RBC_EN>, + <&pciesys CLK_SATA_PM_EN>; + clock-names = "ahb", "axi", "asic", "rbc", "pm"; + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; + status = "disabled";*/ + phys = <&sata_port PHY_TYPE_SATA>; + phy-names = "sata-phy"; + status = "okay"; + }; + + sata_phy: sata-phy@1a243000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a243000 0x0100>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + sata_port: sata-phy@1a243000 { + reg = <0x1a243000 0x0100>; + clocks = <&topckgen CLK_TOP_ETH_500M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>;