From patchwork Mon Aug 10 02:55:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siew Chin Lim X-Patchwork-Id: 1342720 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BQ1Dh0h3cz9sRK for ; Mon, 10 Aug 2020 13:10:28 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BC218821F1; Mon, 10 Aug 2020 05:09:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D461F81BBB; Mon, 10 Aug 2020 04:56:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.3 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, SPF_HELO_NONE,SUBJ_OBFU_PUNCT_FEW,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9C410819E8 for ; Mon, 10 Aug 2020 04:56:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=elly.siew.chin.lim@intel.com IronPort-SDR: PS7SEV+jpke9iNFDtKJlK4SaQ2cdRPeKXR2VGbvwYBzx0gxZNmdNMOIz4GzdyC5j4YblvIxzAq UGOsRAI2//Aw== X-IronPort-AV: E=McAfee;i="6000,8403,9708"; a="141076575" X-IronPort-AV: E=Sophos;i="5.75,456,1589266800"; d="scan'208";a="141076575" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2020 19:56:13 -0700 IronPort-SDR: zB1ACQrQxneTqh6lt/0BItLSJGhCTmX4IqT6sJpqL11JZ1RsLHd8Ab0eaqlkP0gBUkMGSw+QGm R4phVWfSCqfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,456,1589266800"; d="scan'208";a="275883077" Received: from ppglcf0013.png.intel.com ([10.226.229.33]) by fmsmga007.fm.intel.com with ESMTP; 09 Aug 2020 19:56:01 -0700 From: Siew Chin Lim To: u-boot@lists.denx.de Cc: Marek Vasut , Ley Foon Tan , Chin Liang See , Simon Goldschmidt , Chee Hong Ang , Tien Fong Chee , Siew Chin Lim Subject: [PATCH v2] arm: socfpga: soc64: Document down boot_scratch_cold register usage Date: Mon, 10 Aug 2020 10:55:56 +0800 Message-Id: <20200810025556.30975-1-elly.siew.chin.lim@intel.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 10 Aug 2020 05:09:54 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Chin Liang See Document down the usage of boot_scratch_cold register to avoid overlapping of usage in the code for S10 & Agilex. The boot_scratch_cold register is generally used for passing critical system info between SPL, U-Boot and Linux. Signed-off-by: Chin Liang See Signed-off-by: Siew Chin Lim Reviewed-by: Ley Foon Tan --- v2: Mark boot_scratch_cold3 as reserved for customer use. --- arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c90f63a754..e5bb81a7a2 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -46,13 +46,21 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_SOC64_GPO 0xe4 #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 +/* store qspi ref clock */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +/* store osc1 clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +/* store fpga clock freq */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +/* reserved for customer use */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c +/* store PSCI_CPU_ON value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +/* store PSCI_CPU_ON value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +/* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +/* store VBAR_EL3 value */ #define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c #define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 #define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224