From patchwork Thu Aug 6 03:56:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ang, Chee Hong" X-Patchwork-Id: 1341466 X-Patchwork-Delegate: simon.k.r.goldschmidt@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BMZSF05Gpz9sR4 for ; Thu, 6 Aug 2020 13:57:00 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DBBDD81F22; Thu, 6 Aug 2020 05:56:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id EF23281F2D; Thu, 6 Aug 2020 05:56:53 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: * X-Spam-Status: No, score=1.1 required=5.0 tests=AC_FROM_MANY_DOTS,BAYES_00, SPF_HELO_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4885581EF5 for ; Thu, 6 Aug 2020 05:56:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=chee.hong.ang@intel.com IronPort-SDR: zU+gtwqvAhQvrof9eZMzvQIVm4UDUmxX94kCZa5THkdsU2upthrNsEJUCC+s+rztE8C6/vQyY3 eOh6lOyvjH4A== X-IronPort-AV: E=McAfee;i="6000,8403,9704"; a="140312350" X-IronPort-AV: E=Sophos;i="5.75,440,1589266800"; d="scan'208";a="140312350" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2020 20:56:47 -0700 IronPort-SDR: H9IcfdVp5TC5vrWh5HRywGfhAzipCtUMRxZVerb1yNHQNVTDN6whAizVzjhWPGfY4vmY3IrtKJ v9/kWwmDmKjA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,440,1589266800"; d="scan'208";a="323310734" Received: from ppglcf0013.png.intel.com ([10.226.229.33]) by orsmga008.jf.intel.com with ESMTP; 05 Aug 2020 20:56:44 -0700 From: Chee Hong Ang To: u-boot@lists.denx.de Cc: Marek Vasut , Simon Goldschmidt , Tom Rini , Ching Liang See , Ley Foon , Chee Hong Ang , Tien Fong , Siew Chin Subject: [PATCH v2] arm: socfpga: soc64: Check FPGA Config status register before bridge reset Date: Thu, 6 Aug 2020 11:56:29 +0800 Message-Id: <20200806035629.18824-1-chee.hong.ang@intel.com> X-Mailer: git-send-email 2.19.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Instead of querying SDM for FPGA configuration status through mailbox messages, U-Boot now checks System Manager's FPGA Config status register for FPGA configuration status before resetting bridge. Signed-off-by: Chee Hong Ang Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/misc.h | 5 +++++ .../mach-socfpga/include/mach/system_manager_soc64.h | 6 +++++- arch/arm/mach-socfpga/misc_s10.c | 18 ++++++++++-------- 3 files changed, 20 insertions(+), 9 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index a85c5ae..649d2f6 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -39,6 +39,11 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif +#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ + defined(CONFIG_TARGET_SOCFPGA_AGILEX) +int is_fpga_config_ready(void); +#endif + void do_bridge_reset(int enable, unsigned int mask); void socfpga_pl310_clear(void); void socfpga_get_managers_addr(void); diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index c90f63a..5e3f54a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -88,8 +88,12 @@ void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); #define SYSMGR_ECC_OCRAM_EN BIT(0) #define SYSMGR_ECC_OCRAM_SERR BIT(3) #define SYSMGR_ECC_OCRAM_DERR BIT(4) -#define SYSMGR_FPGAINTF_USEFPGA 0x1 +#define SYSMGR_FPGACONFIG_FPGA_COMPLETE BIT(0) +#define SYSMGR_FPGACONFIG_EARLY_USERMODE BIT(1) +#define SYSMGR_FPGACONFIG_READY_MASK (SYSMGR_FPGACONFIG_FPGA_COMPLETE | \ + SYSMGR_FPGACONFIG_EARLY_USERMODE) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 #define SYSMGR_FPGAINTF_NAND BIT(4) #define SYSMGR_FPGAINTF_SDMMC BIT(8) #define SYSMGR_FPGAINTF_SPIM0 BIT(16) diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 670bfa1..52868fb 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -151,17 +151,19 @@ int arch_early_init_r(void) return 0; } +/* Return 1 if FPGA is ready otherwise return 0 */ +int is_fpga_config_ready(void) +{ + return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) & + SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK; +} + void do_bridge_reset(int enable, unsigned int mask) { /* Check FPGA status before bridge enable */ - if (enable) { - int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS); - - if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG) - ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS); - - if (ret) - return; + if (!is_fpga_config_ready()) { + puts("FPGA not ready. Bridge reset aborted!\n"); + return; } socfpga_bridges_reset(enable);