| Message ID | 20200805131557.117409-3-chee.hong.ang@intel.com |
|---|---|
| State | Accepted |
| Commit | b3e2d9fccbe7390a859f7f46001c6312cc35455c |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | Print reset information in SPL | expand |
> -----Original Message----- > From: Ang, Chee Hong <chee.hong.ang@intel.com> > Sent: Wednesday, August 5, 2020 9:16 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; Tom Rini <trini@konsulko.com>; See, > Chin Liang <chin.liang.see@intel.com>; Tan, Ley Foon > <ley.foon.tan@intel.com>; Ang, Chee Hong <chee.hong.ang@intel.com>; > Chee, Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin > <elly.siew.chin.lim@intel.com> > Subject: [PATCH v1 2/2] arm: socfpga: soc64: Show reset state in SPL > > Print reset state (warm/cold) together with the source (watchdog/MPU) > which has triggered the warm reset on S10 & Agilex. > > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> > --- > .../include/mach/reset_manager_soc64.h | 1 + > arch/arm/mach-socfpga/reset_manager_s10.c | 22 > ++++++++++++++++++++++ > arch/arm/mach-socfpga/spl_agilex.c | 1 + > arch/arm/mach-socfpga/spl_s10.c | 1 + > 4 files changed, 25 insertions(+) > Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index fc60f6a..c8bb727 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -8,6 +8,7 @@ void reset_deassert_peripherals_handoff(void); int cpu_has_been_warmreset(void); +void print_reset_info(void); void socfpga_bridges_reset(int enable); #define RSTMGR_SOC64_STATUS 0x00 diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index c743077..9f16bf9 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -104,3 +104,25 @@ int cpu_has_been_warmreset(void) return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK; } + +void print_reset_info(void) +{ + bool iswd; + int n; + u32 stat = cpu_has_been_warmreset(); + + printf("Reset state: %s%s", stat ? "Warm " : "Cold", + (stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : ""); + + stat &= ~RSTMGR_STAT_SDMWARMRST; + if (!stat) { + puts("\n"); + return; + } + + n = generic_ffs(stat) - 1; + iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS); + printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU", + iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) : + (n - RSTMGR_STAT_MPU0RST_BITPOS)); +} diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index bd971ec..0121ff4 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -76,6 +76,7 @@ void board_init_f(ulong dummy) } preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary(); firewall_setup(); diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index b3c6f6a..1f71182 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -81,6 +81,7 @@ void board_init_f(ulong dummy) #endif preloader_console_init(); + print_reset_info(); cm_print_clock_quick_summary(); firewall_setup();
Print reset state (warm/cold) together with the source (watchdog/MPU) which has triggered the warm reset on S10 & Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> --- .../include/mach/reset_manager_soc64.h | 1 + arch/arm/mach-socfpga/reset_manager_s10.c | 22 ++++++++++++++++++++++ arch/arm/mach-socfpga/spl_agilex.c | 1 + arch/arm/mach-socfpga/spl_s10.c | 1 + 4 files changed, 25 insertions(+)