diff mbox series

[v1] spi: cadence-qspi: Fix QSPI write issues

Message ID 20200805093238.136670-1-chee.hong.ang@intel.com
State New
Delegated to: Simon Goldschmidt
Headers show
Series [v1] spi: cadence-qspi: Fix QSPI write issues | expand

Commit Message

Ang, Chee Hong Aug. 5, 2020, 9:32 a.m. UTC
QSPI driver perform chip select on every flash read/write
access. The driver need to disable/enable the QSPI controller
while performing chip select. This may cause some data lost
especially the QSPI controller is configured to run at slower
speed as it may take longer time to access the flash device.
This patch prevent the driver from disable/enable the QSPI
controller too soon and inadvertently halting any ongoing flash
read/write access by ensuring the QSPI controller is always in
idle mode after each read/write access.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 drivers/spi/cadence_qspi_apb.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Tan, Ley Foon Aug. 5, 2020, 10 a.m. UTC | #1
> -----Original Message-----
> From: Ang, Chee Hong <chee.hong.ang@intel.com>
> Sent: Wednesday, August 5, 2020 5:33 PM
> To: u-boot@lists.denx.de
> Cc: Phil Edworthy <PHIL.EDWORTHY@renesas.com>; Vignesh R
> <vigneshr@ti.com>; Tom Rini <trini@konsulko.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>; Ang,
> Chee Hong <chee.hong.ang@intel.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: [PATCH v1] spi: cadence-qspi: Fix QSPI write issues
> 
> QSPI driver perform chip select on every flash read/write access. The driver
> need to disable/enable the QSPI controller while performing chip select. This
> may cause some data lost especially the QSPI controller is configured to run
> at slower speed as it may take longer time to access the flash device.
> This patch prevent the driver from disable/enable the QSPI controller too
> soon and inadvertently halting any ongoing flash read/write access by
> ensuring the QSPI controller is always in idle mode after each read/write
> access.
> 
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 

Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

Regards
Ley Foon
Tan, Ley Foon Aug. 27, 2020, 6:09 a.m. UTC | #2
> -----Original Message-----
> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Tan, Ley Foon
> Sent: Wednesday, August 5, 2020 6:00 PM
> To: Ang, Chee Hong <chee.hong.ang@intel.com>; u-boot@lists.denx.de
> Cc: Phil Edworthy <PHIL.EDWORTHY@renesas.com>; Vignesh R
> <vigneshr@ti.com>; Tom Rini <trini@konsulko.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Chee, Tien Fong <tien.fong.chee@intel.com>;
> Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Subject: RE: [PATCH v1] spi: cadence-qspi: Fix QSPI write issues
> 
> 
> 
> > -----Original Message-----
> > From: Ang, Chee Hong <chee.hong.ang@intel.com>
> > Sent: Wednesday, August 5, 2020 5:33 PM
> > To: u-boot@lists.denx.de
> > Cc: Phil Edworthy <PHIL.EDWORTHY@renesas.com>; Vignesh R
> > <vigneshr@ti.com>; Tom Rini <trini@konsulko.com>; See, Chin Liang
> > <chin.liang.see@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>;
> > Ang, Chee Hong <chee.hong.ang@intel.com>; Chee, Tien Fong
> > <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> > <elly.siew.chin.lim@intel.com>
> > Subject: [PATCH v1] spi: cadence-qspi: Fix QSPI write issues
> >
> > QSPI driver perform chip select on every flash read/write access. The
> > driver need to disable/enable the QSPI controller while performing
> > chip select. This may cause some data lost especially the QSPI
> > controller is configured to run at slower speed as it may take longer time to
> access the flash device.
> > This patch prevent the driver from disable/enable the QSPI controller
> > too soon and inadvertently halting any ongoing flash read/write access
> > by ensuring the QSPI controller is always in idle mode after each
> > read/write access.
> >
> > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> > ---
> >  drivers/spi/cadence_qspi_apb.c | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> 
> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
> 
> Regards
> Ley Foon

+ Jagan, SPI maintainer.

Jagan, can you help integrate this patch?

Regards
Ley Foon
diff mbox series

Patch

diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index f9675f7..5696eb3 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -648,6 +648,10 @@  cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
 	writel(CQSPI_REG_INDIRECTRD_DONE,
 	       plat->regbase + CQSPI_REG_INDIRECTRD);
 
+	/* Wait til QSPI is idle */
+	if (!cadence_qspi_wait_idle(plat->regbase))
+		return -EIO;
+
 	return 0;
 
 failrd:
@@ -763,6 +767,11 @@  cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
 	       plat->regbase + CQSPI_REG_INDIRECTWR);
 	if (bounce_buf)
 		free(bounce_buf);
+
+	/* Wait til QSPI is idle */
+	if (!cadence_qspi_wait_idle(plat->regbase))
+		return -EIO;
+
 	return 0;
 
 failwr: