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Fri, 31 Jul 2020 16:32:05 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 95A9310002A; Fri, 31 Jul 2020 16:32:04 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag6node3.st.com [10.75.127.18]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 84D8F2B1899; Fri, 31 Jul 2020 16:32:04 +0200 (CEST) Received: from localhost (10.75.127.51) by SFHDAG6NODE3.st.com (10.75.127.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 31 Jul 2020 16:32:04 +0200 From: Patrick Delaunay To: CC: Patrick Delaunay , Patrice Chotard , Tom Rini , U-Boot STM32 Subject: [PATCH 10/11] arm: stm32mp: bsec: use IS_ENABLED to prevent ifdef Date: Fri, 31 Jul 2020 16:31:51 +0200 Message-ID: <20200731143152.8812-10-patrick.delaunay@st.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200731143152.8812-1-patrick.delaunay@st.com> References: <20200731143152.8812-1-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG5NODE2.st.com (10.75.127.14) To SFHDAG6NODE3.st.com (10.75.127.18) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-31_05:2020-07-31, 2020-07-31 signatures=0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Use IS_ENABLED to prevent ifdef in bsec driver. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32mp/bsec.c | 86 +++++++++++++++++++----------------- 1 file changed, 46 insertions(+), 40 deletions(-) diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 0c56b440f5..a9b9bd0902 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -74,7 +74,6 @@ static bool bsec_read_lock(u32 address, u32 otp) return !!(readl(address + bank) & bit); } -#ifndef CONFIG_TFABOOT /** * bsec_check_error() - Check status of one otp * @base: base address of bsec IP @@ -279,7 +278,6 @@ static int bsec_program_otp(long base, u32 val, u32 otp) return ret; } -#endif /* CONFIG_TFABOOT */ /* BSEC MISC driver *******************************************************/ struct stm32mp_bsec_platdata { @@ -288,15 +286,17 @@ struct stm32mp_bsec_platdata { static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) { -#ifdef CONFIG_TFABOOT - return stm32_smc(STM32_SMC_BSEC, - STM32_SMC_READ_OTP, - otp, 0, val); -#else - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_platdata *plat; u32 tmp_data = 0; int ret; + if (IS_ENABLED(CONFIG_TFABOOT)) + return stm32_smc(STM32_SMC_BSEC, + STM32_SMC_READ_OTP, + otp, 0, val); + + plat = dev_get_platdata(dev); + /* read current shadow value */ ret = bsec_read_shadow(plat->base, &tmp_data, otp); if (ret) @@ -313,21 +313,22 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp) /* restore shadow value */ ret = bsec_write_shadow(plat->base, tmp_data, otp); + return ret; -#endif } static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp) { -#ifdef CONFIG_TFABOOT - return stm32_smc(STM32_SMC_BSEC, - STM32_SMC_READ_SHADOW, - otp, 0, val); -#else - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_platdata *plat; + + if (IS_ENABLED(CONFIG_TFABOOT)) + return stm32_smc(STM32_SMC_BSEC, + STM32_SMC_READ_SHADOW, + otp, 0, val); + + plat = dev_get_platdata(dev); return bsec_read_shadow(plat->base, val, otp); -#endif } static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) @@ -342,33 +343,38 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp) static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp) { -#ifdef CONFIG_TFABOOT - return stm32_smc_exec(STM32_SMC_BSEC, - STM32_SMC_PROG_OTP, - otp, val); -#else - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_platdata *plat; + + if (IS_ENABLED(CONFIG_TFABOOT)) + return stm32_smc_exec(STM32_SMC_BSEC, + STM32_SMC_PROG_OTP, + otp, val); + + plat = dev_get_platdata(dev); return bsec_program_otp(plat->base, val, otp); -#endif + } static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp) { -#ifdef CONFIG_TFABOOT - return stm32_smc_exec(STM32_SMC_BSEC, - STM32_SMC_WRITE_SHADOW, - otp, val); -#else - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_platdata *plat; + + if (IS_ENABLED(CONFIG_TFABOOT)) + return stm32_smc_exec(STM32_SMC_BSEC, + STM32_SMC_WRITE_SHADOW, + otp, val); + + plat = dev_get_platdata(dev); return bsec_write_shadow(plat->base, val, otp); -#endif } static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) { -#ifdef CONFIG_TFABOOT + if (!IS_ENABLED(CONFIG_TFABOOT)) + return -ENOTSUPP; + if (val == 1) return stm32_smc_exec(STM32_SMC_BSEC, STM32_SMC_WRLOCK_OTP, @@ -377,9 +383,6 @@ static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp) return 0; /* nothing to do */ return -EINVAL; -#else - return -ENOTSUPP; -#endif } static int stm32mp_bsec_read(struct udevice *dev, int offset, @@ -481,18 +484,21 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev) static int stm32mp_bsec_probe(struct udevice *dev) { -#if !defined(CONFIG_TFABOOT) && !defined(CONFIG_SPL_BUILD) int otp; - struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev); + struct stm32mp_bsec_platdata *plat; /* * update unlocked shadow for OTP cleared by the rom code * only executed in U-Boot proper when TF-A is not used */ - for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++) - if (!bsec_read_SR_lock(plat->base, otp)) - bsec_shadow_register(plat->base, otp); -#endif + + if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) { + plat = dev_get_platdata(dev); + + for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++) + if (!bsec_read_SR_lock(plat->base, otp)) + bsec_shadow_register(plat->base, otp); + } return 0; }