From patchwork Fri Jul 24 10:08:41 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 1335566 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=H2yk5HJA; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BClNW1KXRz9sRK for ; Fri, 24 Jul 2020 20:11:39 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BB70D821FD; Fri, 24 Jul 2020 12:10:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1595585424; bh=itwACa8j+gOMswHA0hfKxfaxIEDLtjpbSQQ7gjQLqYw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=H2yk5HJAXxNeKShIsg5D5vR3rdI/mmstQpuIOmXOu7uQCxq9Cch+rkSAoW0iWgyYj B/RjF6vT4l2yuo42iYMFnwTCNnSfG2ugcjBlZWwp3c/UcVdsvAXAevpWAIsuvDbw+6 1EvlfdVpLDsVuveMWV4O3enzBB/DEdaf5nY//qK2nnANDLy9CL2OrfrKphrSut+uf7 Srsrg43lF4AgD4Fk03H8Rc7RPkqVUAN4HViIjDSST1a2Hboq6Z4UGGeIAUoVp4rHnm yMioWKOMcEd/6T/dmILjDJh7tRBRMYKVMkjTb7qRGPgwvOyVGXf05wG9U25N2IMZAJ vLx3mHiuI3HaQ== Received: by phobos.denx.de (Postfix, from userid 109) id D9490821BF; Fri, 24 Jul 2020 12:09:40 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mx2.mailbox.org (mx2a.mailbox.org [IPv6:2001:67c:2050:104:0:2:25:2]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7C5B4821B0 for ; Fri, 24 Jul 2020 12:09:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.2 with cipher ECDHE-RSA-CHACHA20-POLY1305 (256/256 bits)) (No client certificate requested) by mx2.mailbox.org (Postfix) with ESMTPS id 1C1F8A2044; Fri, 24 Jul 2020 12:09:04 +0200 (CEST) Received: from smtp2.mailbox.org ([80.241.60.241]) by gerste.heinlein-support.de (gerste.heinlein-support.de [91.198.250.173]) (amavisd-new, port 10030) with ESMTP id F_hlIGO2M-Ei; Fri, 24 Jul 2020 12:09:00 +0200 (CEST) From: Stefan Roese To: u-boot@lists.denx.de Cc: trini@konsulko.com, sgarapati@marvell.com, awilliams@marvell.com, sjg@chromium.org, cchavva@marvell.com, Bin Meng Subject: [PATCH v1 09/24] pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Date: Fri, 24 Jul 2020 12:08:41 +0200 Message-Id: <20200724100856.1482324-10-sr@denx.de> In-Reply-To: <20200724100856.1482324-1-sr@denx.de> References: <20200724100856.1482324-1-sr@denx.de> MIME-Version: 1.0 X-MBO-SPAM-Probability: 23 X-Rspamd-Score: 3.49 / 15.00 / 15.00 X-Rspamd-Queue-Id: E779E17B2 X-Rspamd-UID: 2b3cbf X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean From: Suneel Garapati Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati Cc: Simon Glass Cc: Bin Meng Signed-off-by: Stefan Roese --- Changes in v1: - Change patch subject - Fixed multi-line comment style - Moved "feature" into new function which is only called, when CONFIG_PCI_SRIOV is enabled, so that the code is not increased in all cases - Changed variable declaration to use reverse xmas tree order drivers/pci/pci-uclass.c | 67 +++++++++++++++++++++++++++++++++++++--- include/pci.h | 3 ++ 2 files changed, 65 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index b0f2b5b77e..5e68a2e306 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1368,14 +1368,55 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, return bus_addr; } +static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off, + struct pci_child_platdata *pdata) +{ + phys_addr_t addr = 0; + + /* + * In the case of a Virtual Function device using BAR + * base and size, add offset for VFn BAR(1, 2, 3...n) + */ + if (pdata->is_virtfn) { + size_t sz; + u32 ea_entry; + + /* MaxOffset, 1st DW */ + dm_pci_read_config32(dev, ea_off + 8, &ea_entry); + sz = ea_entry & PCI_EA_FIELD_MASK; + /* Fill up lower 2 bits */ + sz |= (~PCI_EA_FIELD_MASK); + + if (ea_entry & PCI_EA_IS_64) { + /* MaxOffset 2nd DW */ + dm_pci_read_config32(dev, ea_off + 16, &ea_entry); + sz |= ((u64)ea_entry) << 32; + } + + addr = (pdata->virtid - 1) * (sz + 1); + } + + return addr; +} + static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, - int ea_off) + int ea_off, struct pci_child_platdata *pdata) { int ea_cnt, i, entry_size; int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2; u32 ea_entry; phys_addr_t addr; + if (IS_ENABLED(CONFIG_PCI_SRIOV)) { + /* + * In the case of a Virtual Function device, device is + * Physical function, so pdata will point to required VF + * specific data. + */ + if (pdata->is_virtfn) + bar_id += PCI_EA_BEI_VF_BAR0; + } + /* EA capability structure header */ dm_pci_read_config32(dev, ea_off, &ea_entry); ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK; @@ -1398,6 +1439,9 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, addr |= ((u64)ea_entry) << 32; } + if (IS_ENABLED(CONFIG_PCI_SRIOV)) + addr += dm_pci_map_ea_virt(dev, ea_off, pdata); + /* size ignored for now */ return map_physmem(addr, 0, flags); } @@ -1407,20 +1451,33 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) { + struct pci_child_platdata *pdata = dev_get_parent_platdata(dev); + struct udevice *udev = dev; pci_addr_t pci_bus_addr; u32 bar_response; int ea_off; + if (IS_ENABLED(CONFIG_PCI_SRIOV)) { + /* + * In case of Virtual Function devices, use PF udevice + * as EA capability is defined in Physical Function + */ + if (pdata->is_virtfn) + udev = pdata->pfdev; + } + /* * if the function supports Enhanced Allocation use that instead of * BARs + * Incase of virtual functions, pdata will help read VF BEI + * and EA entry size. */ - ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA); + ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA); if (ea_off) - return dm_pci_map_ea_bar(dev, bar, flags, ea_off); + return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata); /* read BAR address */ - dm_pci_read_config32(dev, bar, &bar_response); + dm_pci_read_config32(udev, bar, &bar_response); pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); /* @@ -1429,7 +1486,7 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) * linear mapping. In the future, this could read the BAR size * and pass that as the size if needed. */ - return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); + return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE); } static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap) diff --git a/include/pci.h b/include/pci.h index 4f4b11df4a..3be642a3ef 100644 --- a/include/pci.h +++ b/include/pci.h @@ -465,6 +465,9 @@ #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ #define PCI_EA_ES 0x00000007 /* Entry Size */ #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ +/* 9-14 map to VF BARs 0-5 respectively */ +#define PCI_EA_BEI_VF_BAR0 9 +#define PCI_EA_BEI_VF_BAR5 14 /* Base, MaxOffset registers */ /* bit 0 is reserved */ #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */