| Message ID | 20200710155313.109533-1-chee.hong.ang@intel.com |
|---|---|
| State | Accepted |
| Commit | 12cc44884b0e74260c2f7396b993f178f8c8df27 |
| Delegated to: | Simon Goldschmidt |
| Headers | show |
| Series | arm: socfpga: soc64: Initialize timer in SPL only | expand |
> -----Original Message----- > From: Ang, Chee Hong <chee.hong.ang@intel.com> > Sent: Friday, July 10, 2020 11:53 PM > To: u-boot@lists.denx.de > Cc: Marek Vasut <marex@denx.de>; Simon Goldschmidt > <simon.k.r.goldschmidt@gmail.com>; See, Chin Liang > <chin.liang.see@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, > Chee Hong <chee.hong.ang@intel.com> > Subject: [PATCH] arm: socfpga: soc64: Initialize timer in SPL only > > Timer only need to be initialized once in SPL. > This patch remove the redundancy of initializing the timer again in U-Boot > proper > > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> > --- Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 3ad98bdb25..7d5598e1a3 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -14,6 +14,7 @@ */ int timer_init(void) { +#ifdef CONFIG_SPL_BUILD int enable = 0x3; /* timer enable + output signal masked */ int loadval = ~0; @@ -22,6 +23,6 @@ int timer_init(void) /* enable processor pysical counter */ asm volatile("msr cntp_ctl_el0, %0" : : "r" (enable)); asm volatile("msr cntp_tval_el0, %0" : : "r" (loadval)); - +#endif return 0; }
Timer only need to be initialized once in SPL. This patch remove the redundancy of initializing the timer again in U-Boot proper Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> --- arch/arm/mach-socfpga/timer_s10.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)