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[2001:871:20f:2c0a:22cf:30ff:fe1a:cea1]) by smtp.gmail.com with ESMTPSA id d26sm484867ejw.89.2020.07.08.14.58.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Jul 2020 14:58:36 -0700 (PDT) From: Johannes Krottmayer To: u-boot@lists.denx.de Cc: kever.yang@rock-chips.com, jagan@amarulasolutions.com, Johannes Krottmayer Subject: [PATCH 1/3] drivers: clk: rockchip: clk_rk3328: Add SPI support Date: Wed, 8 Jul 2020 23:57:38 +0200 Message-Id: <20200708215740.28515-2-krjdev@gmail.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200708215740.28515-1-krjdev@gmail.com> References: <20200708215740.28515-1-krjdev@gmail.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add SPI support for the RK3328 clock driver Signed-off-by: Johannes Krottmayer Cc: Kever Yang Cc: Jagan Teki Reviewed-by: Kever Yang --- drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 02d3b08efa..bf4f1069ea 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) return rk3328_saradc_get_clk(cru); } +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[24]); + div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT; + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) +{ + u32 src_clk_div; + + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[24], + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK, + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT | + (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT); + + return rk3328_spi_get_clk(cru); +} + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3328_saradc_get_clk(priv->cru); break; + case SCLK_SPI: + rate = rk3328_spi_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3328_saradc_set_clk(priv->cru, rate); break; + case SCLK_SPI: + ret = rk3328_spi_set_clk(priv->cru, rate); + break; case DCLK_LCDC: case SCLK_PDM: case SCLK_RTC32K: