| Message ID | 20200708215740.28515-2-krjdev@gmail.com |
|---|---|
| State | Accepted |
| Commit | 19933b66f48ccdf97c4e8542092a1ee814a85097 |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: rk3328: Add SPI support | expand |
On 2020/7/9 上午5:57, Johannes Krottmayer wrote: > Add SPI support for the RK3328 clock driver > > Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> > Cc: Kever Yang <kever.yang@rock-chips.com> > Cc: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c > index 02d3b08efa..bf4f1069ea 100644 > --- a/drivers/clk/rockchip/clk_rk3328.c > +++ b/drivers/clk/rockchip/clk_rk3328.c > @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) > return rk3328_saradc_get_clk(cru); > } > > +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru) > +{ > + u32 div, val; > + > + val = readl(&cru->clksel_con[24]); > + div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT; > + > + return DIV_TO_RATE(OSC_HZ, div); > +} > + > +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) > +{ > + u32 src_clk_div; > + > + src_clk_div = GPLL_HZ / hz; > + assert(src_clk_div < 128); > + > + rk_clrsetreg(&cru->clksel_con[24], > + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK, > + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT | > + (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT); > + > + return rk3328_spi_get_clk(cru); > +} > + > static ulong rk3328_clk_get_rate(struct clk *clk) > { > struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); > @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) > case SCLK_SARADC: > rate = rk3328_saradc_get_clk(priv->cru); > break; > + case SCLK_SPI: > + rate = rk3328_spi_get_clk(priv->cru); > + break; > default: > return -ENOENT; > } > @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) > case SCLK_SARADC: > ret = rk3328_saradc_set_clk(priv->cru, rate); > break; > + case SCLK_SPI: > + ret = rk3328_spi_set_clk(priv->cru, rate); > + break; > case DCLK_LCDC: > case SCLK_PDM: > case SCLK_RTC32K:
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 02d3b08efa..bf4f1069ea 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -555,6 +555,31 @@ static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz) return rk3328_saradc_get_clk(cru); } +static ulong rk3328_spi_get_clk(struct rk3328_cru *cru) +{ + u32 div, val; + + val = readl(&cru->clksel_con[24]); + div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT; + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz) +{ + u32 src_clk_div; + + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div < 128); + + rk_clrsetreg(&cru->clksel_con[24], + CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK, + CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT | + (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT); + + return rk3328_spi_get_clk(cru); +} + static ulong rk3328_clk_get_rate(struct clk *clk) { struct rk3328_clk_priv *priv = dev_get_priv(clk->dev); @@ -581,6 +606,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case SCLK_SARADC: rate = rk3328_saradc_get_clk(priv->cru); break; + case SCLK_SPI: + rate = rk3328_spi_get_clk(priv->cru); + break; default: return -ENOENT; } @@ -617,6 +645,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_SARADC: ret = rk3328_saradc_set_clk(priv->cru, rate); break; + case SCLK_SPI: + ret = rk3328_spi_set_clk(priv->cru, rate); + break; case DCLK_LCDC: case SCLK_PDM: case SCLK_RTC32K:
Add SPI support for the RK3328 clock driver Signed-off-by: Johannes Krottmayer <krjdev@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Jagan Teki <jagan@amarulasolutions.com> --- drivers/clk/rockchip/clk_rk3328.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)