From patchwork Thu Jul 2 21:10:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 1321941 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.a=rsa-sha256 header.s=google header.b=ZnVaGXYR; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yW341Qw4z9sRk for ; Fri, 3 Jul 2020 07:10:39 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DFCF781B9A; Thu, 2 Jul 2020 23:10:34 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=chromium.org header.i=@chromium.org header.b="ZnVaGXYR"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8AC4481B9A; Thu, 2 Jul 2020 23:10:33 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-il1-x143.google.com (mail-il1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D498681BA9 for ; Thu, 2 Jul 2020 23:10:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=chromium.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sjg@chromium.org Received: by mail-il1-x143.google.com with SMTP id t4so12316350iln.1 for ; Thu, 02 Jul 2020 14:10:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T98klmS8gBbJbeSmEMjHG4lLLbPOvHPxKdzK/KwKog0=; b=ZnVaGXYRmYlddfrixGJ454pwrNFgHDctfyFtkQQdSyhMJEs5HKUPZ/CCiWo/ZiDbhW XVlv7JpBwWkqeQjlxaRg0xNUCDzcdEYTyon75CcgpVY66cBq+sUx7/Vsz5mhJArC9LX7 KIK7P1Ixei+Jsf9B9Qu0fyuHOS9ShO+scopPE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T98klmS8gBbJbeSmEMjHG4lLLbPOvHPxKdzK/KwKog0=; b=aQ9z2cTkh6T4pbEOezwAH/wKw9OWsY4qOSMj9C9hcWeqzmkJ8lSmAZ4tpLHsiT9Iai 7BDZ8H1fHvpL5AkOzqUqjmA4KK5YArJ9AViW7zPi+XpLIruDl5alc5SGc9PBI8CwzQYT pkd8Yv2jpoOa1G8gebHZGY3dvL7GKlVuT833uAkosPSJY87Au7TUwC3325nzC+V13Bda NwQ0zU2c71VYZYa9cErFcbGfV/ywekO/pxIG9NBh1I5rwyjoY9QawrkJWiDXt8ekljRD 8yJWOOx3sOChJ5IhQvo9ZdfvhUnWFrufzqsrFPse1S0ze+m2OupLY46kNN6Fm1X7Oj61 Uo4Q== X-Gm-Message-State: AOAM531QQBRsUggCJoPHsEXBU24halmHk/uDnVdKUHNvVw8iiQrfONO9 J2UnXKMYM/Rn4G4fvxEyFHiZjLJIizSg3Q== X-Google-Smtp-Source: ABdhPJyfua2Eq9zvP+9neQGpVQI9Pf7VOysKcJWkA43WpWMgEDY32v4WMV99HBPN95ErYfINvE5Gng== X-Received: by 2002:a92:7b0b:: with SMTP id w11mr14554687ilc.116.1593724226041; Thu, 02 Jul 2020 14:10:26 -0700 (PDT) Received: from localhost.localdomain (c-73-14-175-90.hsd1.co.comcast.net. [73.14.175.90]) by smtp.gmail.com with ESMTPSA id d6sm5525289ilq.27.2020.07.02.14.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2020 14:10:25 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Cc: Simon Goldschmidt , Marek Vasut , Patrick Delaunay , Tom Rini , Heiko Schocher , Walter Lozano , Bin Meng , Jagan Teki , Peng Fan , Heinrich Schuchardt , Masahiro Yamada , Philippe Reynes , Heiko Stuebner , Patrice Chotard , Stefan Roese , Jean-Jacques Hiblot , Simon Glass , Pavel Herrmann Subject: [RFC PATCH v2 2/3] dm: Arch-specific changes for tiny-dm Date: Thu, 2 Jul 2020 15:10:03 -0600 Message-Id: <20200702211004.1491489-3-sjg@chromium.org> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog In-Reply-To: <20200702211004.1491489-1-sjg@chromium.org> References: <20200702211004.1491489-1-sjg@chromium.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Signed-off-by: Simon Glass --- (no changes since v1) arch/arm/dts/rk3288-u-boot.dtsi | 17 ++++-- arch/arm/dts/rk3288-veyron.dtsi | 26 ++++----- arch/arm/dts/rk3288.dtsi | 3 + arch/arm/include/asm/arch-rockchip/clock.h | 9 +++ .../include/asm/arch-rockchip/sdram_rk3288.h | 21 +++++++ arch/arm/include/asm/arch-rockchip/spi.h | 1 + arch/arm/include/asm/io.h | 18 ++++++ arch/arm/mach-rockchip/rk3288/clk_rk3288.c | 46 +++++++++++++++ arch/arm/mach-rockchip/rk3288/rk3288.c | 2 + arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 45 ++++----------- arch/arm/mach-rockchip/sdram.c | 33 ++++++++--- arch/sandbox/cpu/u-boot-spl.lds | 12 ++++ arch/sandbox/dts/sandbox.dts | 3 +- arch/sandbox/dts/sandbox.dtsi | 2 +- arch/x86/cpu/apollolake/cpu_spl.c | 5 +- arch/x86/cpu/apollolake/uart.c | 56 +++++++++++++++++++ arch/x86/dts/chromebook_coral.dts | 1 + arch/x86/lib/tpl.c | 4 +- configs/chromebook_coral_defconfig | 1 + configs/chromebook_jerry_defconfig | 11 ++++ configs/rock2_defconfig | 3 + 21 files changed, 247 insertions(+), 72 deletions(-) diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi index e4e762aabf..d120eed884 100644 --- a/arch/arm/dts/rk3288-u-boot.dtsi +++ b/arch/arm/dts/rk3288-u-boot.dtsi @@ -6,6 +6,11 @@ #include "rockchip-u-boot.dtsi" / { + aliases { + ram0 = &dmc; + clk0 = &cru; + }; + chosen { u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc; @@ -50,6 +55,10 @@ &cru { u-boot,dm-pre-reloc; + + sysreset { + u-boot,dm-pre-reloc; + }; }; &grf { @@ -57,17 +66,13 @@ }; &vopb { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; }; &vopl { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; }; &noc { u-boot,dm-pre-reloc; }; - -&gpio7 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 8754043b9b..9b10eaf1f5 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -10,6 +10,15 @@ #include "rk3288.dtsi" / { + aliases { + spi_flash0 = &spi_flash; + sysreset0 = &sysreset; + syscon0 = &grf; + syscon1 = &sgrf; + syscon2 = &pmu; + syscon3 = &noc; + }; + memory { reg = <0x0 0x80000000>; }; @@ -303,7 +312,7 @@ spi_flash: spiflash@0 { u-boot,dm-pre-reloc; - compatible = "spidev", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ reg = <0>; }; @@ -315,7 +324,6 @@ clock-frequency = <400000>; i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ i2c-scl-rising-time-ns = <100>; /* 45ns measured */ - u-boot,dm-pre-reloc; rk808: pmic@1b { compatible = "rockchip,rk808"; @@ -328,7 +336,6 @@ rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; - u-boot,dm-pre-reloc; vcc1-supply = <&vcc33_sys>; vcc2-supply = <&vcc33_sys>; @@ -601,7 +608,6 @@ }; &pinctrl { - u-boot,dm-pre-reloc; pinctrl-names = "default", "sleep"; pinctrl-0 = < /* Common for sleep and wake, but no owners */ @@ -826,15 +832,3 @@ assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; assigned-clock-parents = <&cru SCLK_OTGPHY0>; }; - -&sdmmc { - u-boot,dm-pre-reloc; -}; - -&gpio3 { - u-boot,dm-pre-reloc; -}; - -&gpio8 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 866fc08215..3983b746f4 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -608,6 +608,9 @@ <150000000>, <75000000>, <300000000>, <150000000>, <75000000>; + sysreset: sysreset { + compatible = "rockchip,sysreset"; + }; }; grf: syscon@ff770000 { diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 22de0aef8d..772d1423ce 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -6,6 +6,9 @@ #ifndef _ASM_ARCH_CLOCK_H #define _ASM_ARCH_CLOCK_H +/* Include this so that struct syscon_uc_info is available for dt-platdata */ +#include + /* define pll mode */ #define RKCLK_PLL_MODE_SLOW 0 #define RKCLK_PLL_MODE_NORMAL 1 @@ -156,10 +159,16 @@ void *rockchip_get_pmucru(void); struct rockchip_cru; struct rk3288_grf; +int rockchip_cru_setup_sysreset(struct udevice *dev); + +int rockchip_cru_setup_tiny_sysreset(struct tinydev *tdev); + void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf); int rockchip_get_clk(struct udevice **devp); +struct tinydev *tiny_rockchip_get_clk(void); + /* * rockchip_reset_bind() - Bind soft reset device as child of clock device * diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h index 9220763fa7..3358584580 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3288.h @@ -8,6 +8,9 @@ #ifndef _ASM_ARCH_RK3288_SDRAM_H__ #define _ASM_ARCH_RK3288_SDRAM_H__ +#include +#include + struct rk3288_sdram_channel { /* * bit width in address, eg: @@ -99,4 +102,22 @@ struct rk3288_base_params { u32 odt; }; +struct rk_chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3288_msch *msch; +}; + +struct rk_dram_info { + struct rk_chan_info chan[2]; + struct ram_info info; + struct clk ddr_clk; + struct tiny_clk tiny_ddr_clk; + struct rockchip_cru *cru; + struct rk3288_grf *grf; + struct rk3288_sgrf *sgrf; + struct rk3288_pmu *pmu; + bool is_veyron; +}; + #endif diff --git a/arch/arm/include/asm/arch-rockchip/spi.h b/arch/arm/include/asm/arch-rockchip/spi.h index a9d210397a..594b0967b5 100644 --- a/arch/arm/include/asm/arch-rockchip/spi.h +++ b/arch/arm/include/asm/arch-rockchip/spi.h @@ -12,6 +12,7 @@ struct rockchip_spi_priv { struct rockchip_spi *regs; struct clk clk; + struct tiny_clk tiny_clk; unsigned int max_freq; unsigned int mode; ulong last_transaction_us; /* Time of last transaction end */ diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 8959749ad6..d26aedd812 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -470,6 +470,24 @@ out: #define isa_check_signature(io,sig,len) (0) #endif /* __mem_isa */ + +/* + * Provide dummy I/O access on ARM, to allow portable code to compile (e.g. the + * ns16550 driver). These functions do nothing and should be guarded by a CONFIG + * on ARM so that they are never executed. + */ +#define outb(val, port) ({ \ + __maybe_unused ulong _val = (val); \ + __maybe_unused ulong _port = (uintptr_t)(port); \ +}) + +#define outw(val, port) outb(val, port) +#define outl(val, port) outb(val, port) + +#define inb(port) ({ __maybe_unused ulong _port = (uintptr_t)(port); 0; }) +#define inw(port) inb(port) +#define inl(port) inb(port) + #endif /* __KERNEL__ */ #include diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index e05bd06a8d..144dfe7256 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -11,6 +11,17 @@ #include #include +static int rockchip_sysreset_probe_(struct sysreset_reg *priv) +{ + priv->glb_srst_fst_value = offsetof(struct rockchip_cru, + cru_glb_srst_fst_value); + priv->glb_srst_snd_value = offsetof(struct rockchip_cru, + cru_glb_srst_snd_value); + + return 0; +} + +#if !CONFIG_IS_ENABLED(TINY_CLK) int rockchip_get_clk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, @@ -31,3 +42,38 @@ void *rockchip_get_cru(void) return priv->cru; } + +int rockchip_cru_setup_sysreset(struct udevice *dev) +{ + struct sysreset_reg *priv = dev_get_priv(dev); + + return rockchip_sysreset_probe_(priv); +} + +#else /* TINY_CLK */ + +struct tinydev *tiny_rockchip_get_clk(void) +{ + return tiny_dev_get(UCLASS_CLK, 0); +} + +void *rockchip_get_cru(void) +{ + struct rk3288_clk_priv *priv; + struct tinydev *tdev; + + tdev = tiny_rockchip_get_clk(); + if (!tdev) + return NULL; + priv = tdev->priv; + + return priv->cru; +} + +int rockchip_cru_setup_tiny_sysreset(struct tinydev *tdev) +{ + struct sysreset_reg *priv = tinydev_get_priv(tdev); + + return rockchip_sysreset_probe_(priv); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index 804abe8a1b..1e7baeea45 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -115,6 +115,7 @@ int rk_board_late_init(void) return rk3288_board_late_init(); } +#if !CONFIG_IS_ENABLED(TINY_CLK) static int do_clock(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -165,3 +166,4 @@ U_BOOT_CMD( "display information about clocks", "" ); +#endif diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index e3da0a0194..52697e9cac 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -10,6 +10,7 @@ #include #include +#if !CONFIG_IS_ENABLED(TINY_SYSCON) static const struct udevice_id rk3288_syscon_ids[] = { { .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC }, { .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF }, @@ -24,40 +25,18 @@ U_BOOT_DRIVER(syscon_rk3288) = { .of_match = rk3288_syscon_ids, }; -#if CONFIG_IS_ENABLED(OF_PLATDATA) -static int rk3288_syscon_bind_of_platdata(struct udevice *dev) -{ - dev->driver_data = dev->driver->of_match->data; - debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); +U_BOOT_DRIVER_ALIAS(syscon_rk3288, rockchip_rk3288_noc) +U_BOOT_DRIVER_ALIAS(syscon_rk3288, rockchip_rk3288_pmu) +U_BOOT_DRIVER_ALIAS(syscon_rk3288, rockchip_rk3288_grf) +U_BOOT_DRIVER_ALIAS(syscon_rk3288, rockchip_rk3288_sgrf) - return 0; -} +#else -U_BOOT_DRIVER(rockchip_rk3288_noc) = { - .name = "rockchip_rk3288_noc", - .id = UCLASS_SYSCON, - .of_match = rk3288_syscon_ids, - .bind = rk3288_syscon_bind_of_platdata, -}; - -U_BOOT_DRIVER(rockchip_rk3288_grf) = { - .name = "rockchip_rk3288_grf", - .id = UCLASS_SYSCON, - .of_match = rk3288_syscon_ids + 1, - .bind = rk3288_syscon_bind_of_platdata, -}; - -U_BOOT_DRIVER(rockchip_rk3288_sgrf) = { - .name = "rockchip_rk3288_sgrf", - .id = UCLASS_SYSCON, - .of_match = rk3288_syscon_ids + 2, - .bind = rk3288_syscon_bind_of_platdata, -}; - -U_BOOT_DRIVER(rockchip_rk3288_pmu) = { - .name = "rockchip_rk3288_pmu", - .id = UCLASS_SYSCON, - .of_match = rk3288_syscon_ids + 3, - .bind = rk3288_syscon_bind_of_platdata, +U_BOOT_TINY_DRIVER(syscon_rk3288) = { + .uclass_id = UCLASS_SYSCON, + .probe = tiny_syscon_setup, +// .ops = &rockchip_clk_tiny_ops, + DM_TINY_PRIV(, \ + sizeof(struct syscon_uc_info)) }; #endif diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 24fe6cc8f0..e4c6644a0f 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -189,15 +189,30 @@ int dram_init(void) struct udevice *dev; int ret; - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; + if (!CONFIG_IS_ENABLED(TINY_RAM)) { + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return log_msg_ret("get", ret); + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return log_msg_ret("info", ret); + } + } else { + struct tinydev *dev; + + dev = tiny_dev_get(UCLASS_RAM, 0); + if (!dev) { + debug("DRAM init failed\n"); + return log_msg_ret("get", -ENOKEY); + } + ret = tiny_ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return log_msg_ret("info", ret); + } } gd->ram_size = ram.size; debug("SDRAM base=%lx, size=%lx\n", diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds index c60eb109b1..c2e3e65721 100644 --- a/arch/sandbox/cpu/u-boot-spl.lds +++ b/arch/sandbox/cpu/u-boot-spl.lds @@ -5,9 +5,21 @@ * found in the LICENSE file. */ +/* Put the tiny devices in the data section since they are changed at runtime */ SECTIONS { + . = ALIGN(4); + .tiny_dev : { + __tiny_dev_start = .; + KEEP(*(SORT(.u_boot_list*tiny_dev*))); + __tiny_dev_end = .; + } +} +INSERT AFTER .data; + +SECTIONS +{ . = ALIGN(4); .u_boot_list : { KEEP(*(SORT(.u_boot_list*))); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 20f6893829..5480c69ebe 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -9,10 +9,11 @@ compatible = "sandbox"; aliases { + axi0 = &axi; i2c0 = &i2c_0; pci0 = &pcic; rtc0 = &rtc_0; - axi0 = &axi; + serial0 = &serial0; spi0 = &spi; }; diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index e1f68cd552..99a6b6328c 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -259,7 +259,7 @@ }; /* Needs to be available prior to relocation */ - uart0: serial { + serial0: serial { u-boot,dm-spl; compatible = "sandbox,serial"; sandbox,text-colour = "cyan"; diff --git a/arch/x86/cpu/apollolake/cpu_spl.c b/arch/x86/cpu/apollolake/cpu_spl.c index 707ceb3e64..0f32ca7dc5 100644 --- a/arch/x86/cpu/apollolake/cpu_spl.c +++ b/arch/x86/cpu/apollolake/cpu_spl.c @@ -171,7 +171,7 @@ static void early_ec_init(void) static int arch_cpu_init_tpl(void) { - struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc; + struct udevice *pmc, *sa, *p2sb, *spi, *lpc; int ret; ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc); @@ -192,9 +192,6 @@ static int arch_cpu_init_tpl(void) if (ret) return log_msg_ret("northbridge", ret); gd->baudrate = CONFIG_BAUDRATE; - ret = uclass_first_device_err(UCLASS_SERIAL, &serial); - if (ret) - return log_msg_ret("serial", ret); if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) { ret = uclass_first_device_err(UCLASS_SPI, &spi); if (ret) diff --git a/arch/x86/cpu/apollolake/uart.c b/arch/x86/cpu/apollolake/uart.c index f368f7d2db..3ab3fc9d4d 100644 --- a/arch/x86/cpu/apollolake/uart.c +++ b/arch/x86/cpu/apollolake/uart.c @@ -8,10 +8,12 @@ */ #include +#include #include #include #include #include +#include #include #include #include @@ -64,6 +66,7 @@ void apl_uart_init(pci_dev_t bdf, ulong base) uart_lpss_init((void *)base); } +#if !CONFIG_IS_ENABLED(TINY_SERIAL) /* * This driver uses its own compatible string but almost everything else from * the standard ns16550 driver. This allows us to provide an of-platdata @@ -132,3 +135,56 @@ U_BOOT_DRIVER(apl_ns16550) = { .ofdata_to_platdata = apl_ns16550_ofdata_to_platdata, .probe = apl_ns16550_probe, }; + +#else /* TINY_SERIAL */ + +static int apl_ns16550_tiny_probe(struct tinydev *tdev) +{ + struct dtd_intel_apl_ns16550 *dtplat = tdev->dtplat; + struct ns16550_platdata *plat = tdev->priv; + ulong base; + pci_dev_t bdf; + + base = dtplat->early_regs[0]; + bdf = pci_ofplat_get_devfn(dtplat->reg[0]); + + if (!CONFIG_IS_ENABLED(PCI)) + apl_uart_init(bdf, base); + + plat->base = base; + plat->reg_shift = dtplat->reg_shift; + plat->reg_width = 1; + plat->clock = dtplat->clock_frequency; + plat->fcr = UART_FCR_DEFVAL; + + return ns16550_tiny_probe_plat(plat); +} + +static int apl_ns16550_tiny_setbrg(struct tinydev *tdev, int baudrate) +{ + struct ns16550_platdata *plat = tdev->priv; + + return ns16550_tiny_setbrg(plat, baudrate); +} + +static int apl_ns16550_tiny_putc(struct tinydev *tdev, const char ch) +{ + struct ns16550_platdata *plat = tdev->priv; + + return ns16550_tiny_putc(plat, ch); +} + +struct tiny_serial_ops apl_ns16550_tiny_ops = { + .probe = apl_ns16550_tiny_probe, + .setbrg = apl_ns16550_tiny_setbrg, + .putc = apl_ns16550_tiny_putc, +}; + +U_BOOT_TINY_DRIVER(apl_ns16550) = { + .uclass_id = UCLASS_SERIAL, + .probe = apl_ns16550_tiny_probe, + .ops = &apl_ns16550_tiny_ops, + DM_TINY_PRIV(, sizeof(struct ns16550_platdata)) +}; + +#endif diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 965d9f387d..f1a1f98c08 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -40,6 +40,7 @@ i2c5 = &i2c_5; i2c6 = &i2c_6; i2c7 = &i2c_7; + serial0 = &serial; }; config { diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index 6f7eb43a17..139de881e8 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -41,7 +41,7 @@ static int x86_tpl_init(void) ret = arch_cpu_init(); if (ret) { debug("%s: arch_cpu_init() failed\n", __func__); - return ret; + return log_msg_ret("arch", ret); } ret = arch_cpu_init_dm(); if (ret) { @@ -59,7 +59,7 @@ void board_init_f(ulong flags) ret = x86_tpl_init(); if (ret) { - debug("Error %d\n", ret); + printf("Error %d\n", ret); panic("x86_tpl_init fail"); } diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig index 79f9b5a232..af8b7a50e8 100644 --- a/configs/chromebook_coral_defconfig +++ b/configs/chromebook_coral_defconfig @@ -102,3 +102,4 @@ CONFIG_CMD_DHRYSTONE=y CONFIG_TPM=y # CONFIG_GZIP is not set # CONFIG_EFI_LOADER is not set +CONFIG_NS16550_DYNAMIC=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 96246b7512..3a44543bc5 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -107,3 +107,14 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_NS16550_DYNAMIC=y +CONFIG_SPL_TINY_ONLY=y +# CONFIG_TINY_CHECK is not set +CONFIG_SPL_TINY_RAM=y +CONFIG_SPL_TINY_SERIAL=y +CONFIG_SPL_TINY_CLK=y +# CONFIG_SPL_CLK_FIXED_RATE is not set +CONFIG_SPL_TINY_SPI=y +CONFIG_SPL_TINY_SPI_FLASH=y +CONFIG_SPL_TINY_SYSRESET=y +CONFIG_SPL_TINY_SYSCON=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 2118402bbe..a458935422 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -83,3 +83,6 @@ CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_CONSOLE_SCROLL_LINES=10 CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +#CONFIG_SPL_TINY_SERIAL=y +#CONFIG_SPL_TINY=y +CONFIG_SPL_OF_PLATDATA=y