From patchwork Wed Jul 1 17:26:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 1321300 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49yFx930Q8z9sPF for ; Thu, 2 Jul 2020 21:19:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7AA7082239; Thu, 2 Jul 2020 13:14:18 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B15498044A; Wed, 1 Jul 2020 19:27:10 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0B24281B4C for ; Wed, 1 Jul 2020 19:27:01 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sebastian.reichel@collabora.com Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sre) with ESMTPSA id C16122A5455 Received: by jupiter.universe (Postfix, from userid 1000) id 20DC3480108; Wed, 1 Jul 2020 19:26:57 +0200 (CEST) From: Sebastian Reichel To: Sebastian Reichel , Stefano Babic , Fabio Estevam , "NXP i.MX U-Boot Team" Cc: Jaehoon Chung , Simon Glass , u-boot@lists.denx.de Subject: [PATCH 05/12] rtc: m41t62: add oscillator fail bit reset support Date: Wed, 1 Jul 2020 19:26:18 +0200 Message-Id: <20200701172625.121978-6-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200701172625.121978-1-sebastian.reichel@collabora.com> References: <20200701172625.121978-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 02 Jul 2020 13:12:53 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean In case of empty battery or glitches the oscillator fail bit might be set. This will reset the bit in the reset routine. Signed-off-by: Sebastian Reichel --- drivers/rtc/m41t62.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/rtc/m41t62.c b/drivers/rtc/m41t62.c index 85d6eb02593f..0a4e12d69827 100644 --- a/drivers/rtc/m41t62.c +++ b/drivers/rtc/m41t62.c @@ -23,6 +23,7 @@ #include #include #include +#include #define M41T62_REG_SSEC 0 #define M41T62_REG_SEC 1 @@ -48,6 +49,7 @@ #define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */ #define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */ #define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */ +#define M41T62_FLAGS_OF (1 << 2) /* OF: Oscillator Flag Bit */ #define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */ #define M41T62_WDAY_SQW_FREQ_MASK 0xf0 @@ -193,6 +195,50 @@ static int m41t62_sqw_set_rate(struct udevice *dev, unsigned int rate) return dm_i2c_write(dev, M41T62_REG_WDAY, &newval, sizeof(newval)); } +static int m41t62_rtc_restart_osc(struct udevice *dev) +{ + u8 val; + int ret; + + /* 0. check if oscillator failure happened */ + ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val)); + if (ret) + return ret; + if (!(val & M41T62_FLAGS_OF)) + return 0; + + ret = dm_i2c_read(dev, M41T62_REG_SEC, &val, sizeof(val)); + if (ret) + return ret; + + /* 1. Set stop bit */ + val |= M41T62_SEC_ST; + ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); + if (ret) + return ret; + + /* 2. Clear stop bit */ + val &= ~M41T62_SEC_ST; + ret = dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val)); + if (ret) + return ret; + + /* 3. wait 4 seconds */ + mdelay(4000); + + ret = dm_i2c_read(dev, M41T62_REG_FLAGS, &val, sizeof(val)); + if (ret) + return ret; + + /* 4. clear M41T62_FLAGS_OF bit */ + val &= ~M41T62_FLAGS_OF; + ret = dm_i2c_write(dev, M41T62_REG_FLAGS, &val, sizeof(val)); + if (ret) + return ret; + + return 0; +} + static int m41t62_rtc_clear_ht(struct udevice *dev) { u8 val; @@ -218,6 +264,10 @@ static int m41t62_rtc_reset(struct udevice *dev) { int ret; + ret = m41t62_rtc_restart_osc(dev); + if (ret) + return ret; + ret = m41t62_rtc_clear_ht(dev); if (ret) return ret;