diff mbox series

[v2,4/5] mips: cache: Make invalidate_dcache_range() weak to enable overwrite

Message ID 20200630103320.1290545-5-sr@denx.de
State Awaiting Upstream
Delegated to: Daniel Schwierzeck
Headers show
Series mips: Improve initial Octeon MIPS64 support | expand

Commit Message

Stefan Roese June 30, 2020, 10:33 a.m. UTC
This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.

Signed-off-by: Stefan Roese <sr@denx.de>
---

(no changes since v1)

 arch/mips/lib/cache.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Daniel Schwierzeck July 11, 2020, 10:45 p.m. UTC | #1
> This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
> makes it possible to overwrite this function by a platforms specific
> version, which will be done for Octeon.
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> ---
> 
> (no changes since v1)
> 
>  arch/mips/lib/cache.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> 

applied to u-boot-mips/next, thanks.


Stefan, I'll apply the two Octeon MIPS64 base support series after
I have applied my start.S refactoring and header sync series.
Stefan Roese July 16, 2020, 6:24 a.m. UTC | #2
Hi Daniel,

On 12.07.20 00:45, Daniel Schwierzeck wrote:
>> This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
>> makes it possible to overwrite this function by a platforms specific
>> version, which will be done for Octeon.
>>
>> Signed-off-by: Stefan Roese <sr@denx.de>
>> ---
>>
>> (no changes since v1)
>>
>>   arch/mips/lib/cache.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>>
> 
> applied to u-boot-mips/next, thanks.
> 
> 
> Stefan, I'll apply the two Octeon MIPS64 base support series after
> I have applied my start.S refactoring and header sync series.

Thanks a lot.

Thanks,
Stefan
diff mbox series

Patch

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index ad37f05802..cf29994a7a 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -159,7 +159,7 @@  void __weak flush_dcache_range(ulong start_addr, ulong stop)
 	sync();
 }
 
-void invalidate_dcache_range(ulong start_addr, ulong stop)
+void __weak invalidate_dcache_range(ulong start_addr, ulong stop)
 {
 	unsigned long lsize = dcache_line_size();
 	unsigned long slsize = scache_line_size();