diff mbox series

[v2,1/5] mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init code

Message ID 20200630103320.1290545-2-sr@denx.de
State Accepted
Delegated to: Daniel Schwierzeck
Headers show
Series mips: Improve initial Octeon MIPS64 support | expand

Commit Message

Stefan Roese June 30, 2020, 10:33 a.m. UTC 
This patch adds the optional call to mips_mach_early_init() to start.S
at a very early stage. Its disabled per default. It can be used for
very early machine / platform specific init code.  Its called very
early and at this stage the PC is allowed to differ from the linking
address (CONFIG_TEXT_BASE) as no absolute jump has been performed until
this call.

It will be used by thje Octeon platform.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
---

(no changes since v1)

 arch/mips/Kconfig     | 9 +++++++++
 arch/mips/cpu/start.S | 5 +++++
 2 files changed, 14 insertions(+)
diff mbox series

Patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index dd56da6dae..327fd4848a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -296,6 +296,15 @@  config MIPS_CACHE_INDEX_BASE
 	  Normally this is CKSEG0. If the MIPS system needs to move this block
 	  to some SRAM or ScratchPad RAM, adapt this option accordingly.
 
+config MIPS_MACH_EARLY_INIT
+	bool "Enable mach specific very early init code"
+	help
+	  Use this to enable the call to mips_mach_early_init() very early
+	  from start.S. This function can be used e.g. to do some very early
+	  CPU / SoC intitialization or image copying. Its called very early
+	  and at this stage the PC might not match the linking address
+	  (CONFIG_TEXT_BASE) - no absolute jump done until this call.
+
 config MIPS_CACHE_SETUP
 	bool "Enable startup code to initialize and setup caches"
 	default n if SKIP_LOWLEVEL_INIT
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
index 08dddbdf5f..a7190ec3b2 100644
--- a/arch/mips/cpu/start.S
+++ b/arch/mips/cpu/start.S
@@ -195,6 +195,11 @@  wr_done:
 	/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
 	mtc0	zero, CP0_COMPARE
 
+#ifdef CONFIG_MIPS_MACH_EARLY_INIT
+	bal	mips_mach_early_init
+	 nop
+#endif
+
 #ifdef CONFIG_MIPS_CACHE_SETUP
 	/* Disable caches */
 	PTR_LA	t9, mips_cache_disable