diff mbox series

arm64: ls1043a: Remove the workaround of erratum A-009929

Message ID 20200625142353.31301-1-Zhiqiang.Hou@nxp.com
State Awaiting Upstream
Delegated to: Priyanka Jain
Headers show
Series arm64: ls1043a: Remove the workaround of erratum A-009929 | expand

Commit Message

Zhiqiang Hou June 25, 2020, 2:23 p.m. UTC
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The workaround has been implemented in PBI phase, so remove
the duplicated implementation from U-Boot.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig |  4 ----
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 15 ---------------
 2 files changed, 19 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 2f75b2cdd3..75c13927de 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -67,7 +67,6 @@  config ARCH_LS1043A
 	select SYS_FSL_ERRATUM_A009660 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009663 if !TFABOOT
 	select SYS_FSL_ERRATUM_A009798
-	select SYS_FSL_ERRATUM_A009929
 	select SYS_FSL_ERRATUM_A009942 if !TFABOOT
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A010539
@@ -591,9 +590,6 @@  config SYS_FSL_ERRATUM_A009635
 config SYS_FSL_ERRATUM_A009660
 	bool
 
-config SYS_FSL_ERRATUM_A009929
-	bool
-
 config SYS_FSL_ERRATUM_A050382
 	bool
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index ad7ea05935..0cd8e92e81 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -445,20 +445,6 @@  int get_core_volt_from_fuse(void)
 }
 
 #elif defined(CONFIG_FSL_LSCH2)
-
-static void erratum_a009929(void)
-{
-#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
-	struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
-	u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
-	u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
-
-	rstrqmr1 |= 0x00000400;
-	gur_out32(&gur->rstrqmr1, rstrqmr1);
-	writel(0x01000000, dcsr_cop_ccp);
-#endif
-}
-
 /*
  * This erratum requires setting a value to eddrtqcr1 to optimal
  * the DDR performance. The eddrtqcr1 register is in SCFG space
@@ -724,7 +710,6 @@  void fsl_lsch2_early_init_f(void)
 #endif
 	/* Erratum */
 	erratum_a008850_early(); /* part 1 of 2 */
-	erratum_a009929();
 	erratum_a009660();
 	erratum_a010539();
 	erratum_a009008();