diff mbox series

[1/2] arm: mvebu: a38x: Fix typo

Message ID 20200625004851.21056-2-judge.packham@gmail.com
State Awaiting Upstream
Delegated to: Stefan Roese
Headers show
Series arm: mvebu: a38x: USB2 serdes changes | expand

Commit Message

Chris Packham June 25, 2020, 12:48 a.m. UTC
Fix spelling of Alignment.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
---

 arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Stefan Roese June 29, 2020, 12:09 p.m. UTC | #1
On 25.06.20 02:48, Chris Packham wrote:
> Fix spelling of Alignment.
> 
> Signed-off-by: Chris Packham <judge.packham@gmail.com>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

> ---
> 
>   arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> index 67a00cf1cf7b..d4480622c89c 100644
> --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
> @@ -533,7 +533,7 @@ struct op_params pex_and_usb3_tx_config_params3[] = {
>   struct op_params pex_by4_config_params[] = {
>   	/* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
>   	{GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
> -	/* Lane Alignement enable */
> +	/* Lane Alignment enable */
>   	{LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
>   	/* Max PLL phy config */
>   	{CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},
>
diff mbox series

Patch

diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
index 67a00cf1cf7b..d4480622c89c 100644
--- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
+++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c
@@ -533,7 +533,7 @@  struct op_params pex_and_usb3_tx_config_params3[] = {
 struct op_params pex_by4_config_params[] = {
 	/* unit_base_reg, unit_offset, mask, data, wait_time, num_of_loops */
 	{GLOBAL_CLK_SRC_HI, 0x800, 0x7, {0x5, 0x0, 0x0, 0x2}, 0, 0},
-	/* Lane Alignement enable */
+	/* Lane Alignment enable */
 	{LANE_ALIGN_REG0, 0x800, 0x1000, {0x0, 0x0, 0x0, 0x0}, 0, 0},
 	/* Max PLL phy config */
 	{CALIBRATION_CTRL_REG, 0x800, 0x1000, {0x1000, 0x1000, 0x1000, 0x1000},