From patchwork Mon Jun 1 19:53:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1301914 X-Patchwork-Delegate: priyanka.jain@nxp.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.a=rsa-sha256 header.s=mail2016061301 header.b=LU1LSxq0; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 49bQt161Tlz9sWM for ; Tue, 2 Jun 2020 05:56:41 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C78448194A; Mon, 1 Jun 2020 21:54:38 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; secure) header.d=walle.cc header.i=@walle.cc header.b="LU1LSxq0"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 1954581260; Mon, 1 Jun 2020 21:54:11 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8A61A812EC for ; Mon, 1 Jun 2020 21:53:51 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=michael@walle.cc Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id D22B222F54; Mon, 1 Jun 2020 21:53:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1591041231; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=tOiNUeYZvdQwr2Co7wx+Ej33oJpTJf49+gmvKe/9Qjk=; b=LU1LSxq06SPT4MVyXeG+7wOGplUvm/pG4gqtLaXYsm8slFZ62n7bVGPLAXWkc1iORFg907 yzXTDepwEAyh82Yu5tceAXBDUDlZiEhVpUiTmDfrsGYHcEwo2AvELj9DPHqPOxyS5CvZhz iecj71Sr6L1jAF3OLslzICy9c1BwXGY= From: Michael Walle To: u-boot@lists.denx.de Cc: Udit Kumar , Meenakshi Aggarwal , Prabhakar Kushwaha , Priyanka Jain , Tom Rini , Heinrich Schuchardt , Michael Walle Subject: [PATCH v2 13/13] armv8: layerscape: rework spin table Date: Mon, 1 Jun 2020 21:53:36 +0200 Message-Id: <20200601195336.3237-14-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200601195336.3237-1-michael@walle.cc> References: <20200601195336.3237-1-michael@walle.cc> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.30rc1 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.2 at phobos.denx.de X-Virus-Status: Clean There are two issues: (1) The spin table doesn't convert the endianness of the jump address. Although there is code for it, the result isn't used at all (x0). (2) If something goes wrong, the function returns. But that doesn't make sense at all. Use the actual converted jump address as destination to fix. If there is an error, jump to a trap loop. And rearrange the code exception level switching code to make it smaller and clearer. This reduces the size of the spin table code section from 696 bytes to 424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696 bytes to 632 bytes. Signed-off-by: Michael Walle --- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 83 +++++-------------- 1 file changed, 23 insertions(+), 60 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index f082e10231..363ded03e6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -31,7 +31,7 @@ __spin_table: .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE .align 2 -ENTRY(__secondary_boot_func) +__secondary_boot_func: /* * MPIDR_EL1 Fields: * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1) @@ -72,73 +72,36 @@ ENTRY(__secondary_boot_func) str x4, [x11, #8] /* STATUS */ dsb sy -slave_cpu: +1: wfe - ldr x0, [x11] - cbz x0, slave_cpu -#ifndef CONFIG_ARMV8_SWITCH_TO_EL1 + ldr x4, [x11] + cbz x4, 1b mrs x1, sctlr_el2 -#else - mrs x1, sctlr_el1 -#endif - tbz x1, #25, cpu_is_le - rev x0, x0 /* BE to LE conversion */ -cpu_is_le: - ldr x5, [x11, #24] - cbz x5, 1f - + tbz x1, #25, 2f + rev x4, x4 /* BE to LE conversion */ +2: + ldr x6, =ES_TO_AARCH64 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 - ldr x5, =ES_TO_AARCH64 -#else - ldr x4, [x11] - ldr x5, =ES_TO_AARCH32 + adr x5, 3f + switch_el x7, 0f, _dead_loop, _dead_loop +0: armv8_switch_to_el2_m x5, x6, x7 #endif - bl secondary_switch_to_el2 - -1: +3: + ldr x7, [x11, #24] /* ARCH_COMP */ + cbz x7, 4f + ldr x6, =ES_TO_AARCH32 +4: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 - adr x4, secondary_switch_to_el1 + switch_el x7, _dead_loop, 0f, _dead_loop +0: armv8_switch_to_el1_m x4, x6, x7 #else - ldr x4, [x11] + switch_el x7, 0f, _dead_loop, _dead_loop +0: armv8_switch_to_el2_m x4, x6, x7 #endif - ldr x5, =ES_TO_AARCH64 - bl secondary_switch_to_el2 - -ENDPROC(__secondary_boot_func) - -ENTRY(secondary_switch_to_el2) - switch_el x6, 1f, 0f, 0f -0: ret -1: armv8_switch_to_el2_m x4, x5, x6 -ENDPROC(secondary_switch_to_el2) - -ENTRY(secondary_switch_to_el1) - mrs x0, mpidr_el1 - ubfm x1, x0, #8, #15 - ubfm x2, x0, #0, #1 - orr x10, x2, x1, lsl #2 /* x10 has LPID */ - - lsl x1, x10, #6 - adr x0, __spin_table - /* physical address of this cpus spin table element */ - add x11, x1, x0 - - ldr x4, [x11] - - ldr x5, [x11, #24] - cbz x5, 2f - ldr x5, =ES_TO_AARCH32 - bl switch_to_el1 - -2: ldr x5, =ES_TO_AARCH64 - -switch_to_el1: - switch_el x6, 0f, 1f, 0f -0: ret -1: armv8_switch_to_el1_m x4, x5, x6 -ENDPROC(secondary_switch_to_el1) +_dead_loop: + wfe + b _dead_loop /* Ensure that the literals used by the secondary boot code are * assembled within it (this is required so that we can protect